ID_ISAR1, Instruction Set Attribute Register 1
The ID_ISAR1 characteristics are:
Purpose
Provides information about the instruction sets implemented by the PE in AArch32 state.
Must be interpreted with ID_ISAR0, ID_ISAR2, ID_ISAR3, ID_ISAR4, and ID_ISAR5.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section G7.1.3.
Configuration
AArch32 System register ID_ISAR1 bits [31:0] are architecturally mapped to AArch64 System register ID_ISAR1_EL1[31:0] .
Attributes
ID_ISAR1 is a 32-bit register.
Field descriptions
The ID_ISAR1 bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Jazelle | Interwork | Immediate | IfThen | Extend | Except_AR | Except | Endian | ||||||||||||||||||||||||
Jazelle, bits [31:28]
Indicates the implemented Jazelle extension instructions. Defined values are:
| Jazelle | Meaning |
|---|---|
| 0b0000 |
No support for Jazelle. |
| 0b0001 |
Adds the BXJ instruction, and the J bit in the PSR. This setting might indicate a trivial implementation of the Jazelle extension. |
All other values are reserved.
In Armv8-A the only permitted value is 0b0001.
Interwork, bits [27:24]
Indicates the implemented Interworking instructions. Defined values are:
| Interwork | Meaning |
|---|---|
| 0b0000 |
None implemented. |
| 0b0001 |
Adds the BX instruction, and the T bit in the PSR. |
| 0b0010 |
As for 0b0001, and adds the BLX instruction. PC loads have BX-like behavior. |
| 0b0011 |
As for 0b0010, and guarantees that data-processing instructions in the A32 instruction set with the PC as the destination and the S bit clear have BX-like behavior. |
All other values are reserved.
In Armv8-A the only permitted value is 0b0011.
Immediate, bits [23:20]
Indicates the implemented data-processing instructions with long immediates. Defined values are:
| Immediate | Meaning |
|---|---|
| 0b0000 |
None implemented. |
| 0b0001 |
Adds:
|
All other values are reserved.
In Armv8-A the only permitted value is 0b0001.
IfThen, bits [19:16]
Indicates the implemented If-Then instructions in the T32 instruction set. Defined values are:
| IfThen | Meaning |
|---|---|
| 0b0000 |
None implemented. |
| 0b0001 |
Adds the IT instructions, and the IT bits in the PSRs. |
All other values are reserved.
In Armv8-A the only permitted value is 0b0001.
Extend, bits [15:12]
Indicates the implemented Extend instructions. Defined values are:
| Extend | Meaning |
|---|---|
| 0b0000 |
No scalar sign-extend or zero-extend instructions are implemented, where scalar instructions means non-Advanced SIMD instructions. |
| 0b0001 |
Adds the SXTB, SXTH, UXTB, and UXTH instructions. |
| 0b0010 |
As for 0b0001, and adds the SXTB16, SXTAB, SXTAB16, SXTAH, UXTB16, UXTAB, UXTAB16, and UXTAH instructions. |
All other values are reserved.
In Armv8-A the only permitted value is 0b0010.
Except_AR, bits [11:8]
Indicates the implemented A and R profile exception-handling instructions. Defined values are:
| Except_AR | Meaning |
|---|---|
| 0b0000 |
None implemented. |
| 0b0001 |
Adds the SRS and RFE instructions, and the A and R profile forms of the CPS instruction. |
All other values are reserved.
In Armv8-A the only permitted value is 0b0001.
Except, bits [7:4]
Indicates the implemented exception-handling instructions in the A32 instruction set. Defined values are:
| Except | Meaning |
|---|---|
| 0b0000 |
Not implemented. This indicates that the User bank and Exception return forms of the LDM and STM instructions are not implemented. |
| 0b0001 |
Adds the LDM (exception return), LDM (user registers), and STM (user registers) instruction versions. |
All other values are reserved.
In Armv8-A the only permitted value is 0b0001.
Endian, bits [3:0]
Indicates the implemented Endian instructions. Defined values are:
| Endian | Meaning |
|---|---|
| 0b0000 |
None implemented. |
| 0b0001 |
Adds the SETEND instruction, and the E bit in the PSRs. |
All other values are reserved.
In Armv8-A the permitted values are 0b0000 and 0b0001.
Accessing the ID_ISAR1
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0000 | 0b0010 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID3 == '1' then
AArch32.TakeHypTrapException(0x03);
else
return ID_ISAR1;
elsif PSTATE.EL == EL2 then
return ID_ISAR1;
elsif PSTATE.EL == EL3 then
return ID_ISAR1;