ID_ISAR5, Instruction Set Attribute Register 5
The ID_ISAR5 characteristics are:
Purpose
Provides information about the instruction sets implemented by the PE in AArch32 state.
Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, and ID_ISAR4.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section G7.1.3.
Configuration
AArch32 System register ID_ISAR5 bits [31:0] are architecturally mapped to AArch64 System register ID_ISAR5_EL1[31:0] .
Attributes
ID_ISAR5 is a 32-bit register.
Field descriptions
The ID_ISAR5 bit assignments are:
VCMA, bits [31:28]
From Armv8.3:
From Armv8.3:
Indicates AArch32 support for complex number addition and multiplication where numbers are stored in vectors. Defined values are:
VCMA | Meaning |
---|---|
0b0000 |
The VCMLA and VCADD instructions are not implemented in AArch32. |
0b0001 |
The VCMLA and VCADD instructions are implemented in AArch32. |
All other values are reserved.
In Armv8.0, Armv8.1 and Armv8.2 the only permitted value is 0b0000.
From Armv8.3 the only permitted value is 0b0001. This feature is identified as ARMv8.3-CompNum.
Otherwise:
Otherwise:
Reserved, RES0.
RDM, bits [27:24]
From Armv8.1:
From Armv8.1:
Indicates whether the VQRDMLAH and VQRDMLSH instructions are implemented in AArch32 state. Defined values are:
RDM | Meaning |
---|---|
0b0000 |
No VQRDMLAH and VQRDMLSH instructions implemented. |
0b0001 |
VQRDMLAH and VQRDMLSH instructions implemented. |
All other values are reserved.
ARMv8.1-RDMA implements the functionality identified by the value 0b0001.
From Armv8.1 the only permitted value is 0b0001.
Otherwise:
Otherwise:
Reserved, RES0.
Bits [23:20]
Reserved, RES0.
CRC32, bits [19:16]
Indicates whether the CRC32 instructions are implemented in AArch32 state.
CRC32 | Meaning |
---|---|
0b0000 |
No CRC32 instructions implemented. |
0b0001 |
CRC32B, CRC32H, CRC32W, CRC32CB, CRC32CH, and CRC32CW instructions implemented. |
All other values are reserved.
In Armv8.0 the permitted values are 0b0000 and 0b0001.
From Armv8.1 the only permitted value is 0b0001.
SHA2, bits [15:12]
Indicates whether the SHA2 instructions are implemented in AArch32 state.
SHA2 | Meaning |
---|---|
0b0000 |
No SHA2 instructions implemented. |
0b0001 |
SHA256H, SHA256H2, SHA256SU0, and SHA256SU1 implemented. |
All other values are reserved.
In Armv8-A the permitted values are 0b0000 and 0b0001.
SHA1, bits [11:8]
Indicates whether the SHA1 instructions are implemented in AArch32 state.
SHA1 | Meaning |
---|---|
0b0000 |
No SHA1 instructions implemented. |
0b0001 |
SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 implemented. |
All other values are reserved.
In Armv8-A the permitted values are 0b0000 and 0b0001.
AES, bits [7:4]
Indicates whether the AES instructions are implemented in AArch32 state.
AES | Meaning |
---|---|
0b0000 |
No AES instructions implemented. |
0b0001 |
AESE, AESD, AESMC, and AESIMC implemented. |
0b0010 |
As for 0b0001, plus VMULL (polynomial) instructions operating on 64-bit data quantities. |
All other values are reserved.
In Armv8-A the permitted values are 0b0000 and 0b0010.
SEVL, bits [3:0]
Indicates whether the SEVL instruction is implemented in AArch32 state.
SEVL | Meaning |
---|---|
0b0000 |
SEVL is implemented as a NOP. |
0b0001 |
SEVL is implemented as Send Event Local. |
All other values are reserved.
In Armv8-A the only permitted value is 0b0001.
Accessing the ID_ISAR5
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0000 | 0b0010 | 0b101 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID3 == '1' then AArch32.TakeHypTrapException(0x03); else return ID_ISAR5; elsif PSTATE.EL == EL2 then return ID_ISAR5; elsif PSTATE.EL == EL3 then return ID_ISAR5;