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HFGITR_EL2, Hypervisor Fine-Grained Instruction Trap Register

The HFGITR_EL2 characteristics are:

Purpose

Provides controls for traps of execution of System instructions.

Configuration

This register is present only when ARMv8.6-FGT is implemented. Otherwise, direct accesses to HFGITR_EL2 are UNDEFINED.

Some or all RW fields of this register have defined reset values. These apply only if the PE resets into EL2 using AArch64. Otherwise, RW fields in this register reset to architecturally UNKNOWN values.

Attributes

HFGITR_EL2 is a 64-bit register.

Field descriptions

The HFGITR_EL2 bit assignments are:

Bits [63:55]

Reserved, RES0.

DCCVAC, bit [54]

Trap execution of multiple System instructions. Enables a trap on execution at EL1 and EL0 using AArch64 of any of the following AArch64 System instructions to EL2:

DCCVACMeaning
0b0

Execution of the System instructions listed above is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 and EL0 using AArch64 of any of the System instructions listed above is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

SVC_EL1, bit [53]

Trap execution of SVC at EL1 using AArch64 to EL2.

SVC_EL1Meaning
0b0

Execution of SVC is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of SVC at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x15, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

SVC_EL0, bit [52]

Trap execution of SVC at EL0 using AArch64 and execution of SVC at EL0 using AArch32 when EL1 is using AArch64 to EL2.

SVC_EL0Meaning
0b0

Execution of SVC at EL0 using AArch64 and execution of SVC at EL0 using AArch32 is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the instruction generates a higher priority exception:

  • Execution of SVC at EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x15.
  • Execution of SVC at EL0 using AArch32 is trapped to EL2 and reported with EC syndrome value 0x11.

In a system where the PE resets into EL2, this field resets to 0.

ERET, bit [51]

Trap execution of multiple System instructions. Enables a trap on execution at EL1 using AArch64 of any of the following AArch64 System instructions to EL2:

  • ERET.
  • ERETAA, if ARMv8.3-PAuth is implemented.
  • ERETAB, if ARMv8.3-PAuth is implemented.
ERETMeaning
0b0

Execution of the System instructions listed above is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 using AArch64 of any of the System instructions listed above is trapped to EL2 and reported with EC syndrome value 0x1A, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

CPPRCTX, bit [50]

When ARMv8.0-PredInv is implemented:

Trap execution of CPP RCTX at EL1 and EL0 using AArch64 and execution of CPPRCTX at EL0 using AArch32 when EL1 is using AArch64 to EL2.

CPPRCTXMeaning
0b0

Execution of CPP RCTX at EL1 and EL0 using AArch64 and execution of CPPRCTX at EL0 using AArch32 is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the instruction generates a higher priority exception:

  • Execution of CPP RCTX at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18.
  • Execution of CPPRCTX at EL0 using AArch32 is trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

DVPRCTX, bit [49]

When ARMv8.0-PredInv is implemented:

Trap execution of DVP RCTX at EL1 and EL0 using AArch64 and execution of DVPRCTX at EL0 using AArch32 when EL1 is using AArch64 to EL2.

DVPRCTXMeaning
0b0

Execution of DVP RCTX at EL1 and EL0 using AArch64 and execution of DVPRCTX at EL0 using AArch32 is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the instruction generates a higher priority exception:

  • Execution of DVP RCTX at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18.
  • Execution of DVPRCTX at EL0 using AArch32 is trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

CFPRCTX, bit [48]

When ARMv8.0-PredInv is implemented:

Trap execution of CFP RCTX at EL1 and EL0 using AArch64 and execution of CFPRCTX at EL0 using AArch32 when EL1 is using AArch64 to EL2.

CFPRCTXMeaning
0b0

Execution of CFP RCTX at EL1 and EL0 using AArch64 and execution of CFPRCTX at EL0 using AArch32 is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the instruction generates a higher priority exception:

  • Execution of CFP RCTX at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18.
  • Execution of CFPRCTX at EL0 using AArch32 is trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TLBIVAALE1, bit [47]

Trap execution of TLBI VAALE1 at EL1 using AArch64 to EL2.

TLBIVAALE1Meaning
0b0

Execution of TLBI VAALE1 is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VAALE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

TLBIVALE1, bit [46]

Trap execution of TLBI VALE1 at EL1 using AArch64 to EL2.

TLBIVALE1Meaning
0b0

Execution of TLBI VALE1 is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VALE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

TLBIVAAE1, bit [45]

Trap execution of TLBI VAAE1 at EL1 using AArch64 to EL2.

TLBIVAAE1Meaning
0b0

Execution of TLBI VAAE1 is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VAAE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

TLBIASIDE1, bit [44]

Trap execution of TLBI ASIDE1 at EL1 using AArch64 to EL2.

TLBIASIDE1Meaning
0b0

Execution of TLBI ASIDE1 is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI ASIDE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

TLBIVAE1, bit [43]

Trap execution of TLBI VAE1 at EL1 using AArch64 to EL2.

TLBIVAE1Meaning
0b0

Execution of TLBI VAE1 is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VAE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

TLBIVMALLE1, bit [42]

Trap execution of TLBI VMALLE1 at EL1 using AArch64 to EL2.

TLBIVMALLE1Meaning
0b0

Execution of TLBI VMALLE1 is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VMALLE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

TLBIRVAALE1, bit [41]

When ARMv8.4-TLBI is implemented:

Trap execution of TLBI RVAALE1 at EL1 using AArch64 to EL2.

TLBIRVAALE1Meaning
0b0

Execution of TLBI RVAALE1 is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVAALE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TLBIRVALE1, bit [40]

When ARMv8.4-TLBI is implemented:

Trap execution of TLBI RVALE1 at EL1 using AArch64 to EL2.

TLBIRVALE1Meaning
0b0

Execution of TLBI RVALE1 is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVALE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TLBIRVAAE1, bit [39]

When ARMv8.4-TLBI is implemented:

Trap execution of TLBI RVAAE1 at EL1 using AArch64 to EL2.

TLBIRVAAE1Meaning
0b0

Execution of TLBI RVAAE1 is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVAAE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TLBIRVAE1, bit [38]

When ARMv8.4-TLBI is implemented:

Trap execution of TLBI RVAE1 at EL1 using AArch64 to EL2.

TLBIRVAE1Meaning
0b0

Execution of TLBI RVAE1 is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVAE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TLBIRVAALE1IS, bit [37]

When ARMv8.4-TLBI is implemented:

Trap execution of TLBI RVAALE1IS at EL1 using AArch64 to EL2.

TLBIRVAALE1ISMeaning
0b0

Execution of TLBI RVAALE1IS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVAALE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TLBIRVALE1IS, bit [36]

When ARMv8.4-TLBI is implemented:

Trap execution of TLBI RVALE1IS at EL1 using AArch64 to EL2.

TLBIRVALE1ISMeaning
0b0

Execution of TLBI RVALE1IS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVALE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TLBIRVAAE1IS, bit [35]

When ARMv8.4-TLBI is implemented:

Trap execution of TLBI RVAAE1IS at EL1 using AArch64 to EL2.

TLBIRVAAE1ISMeaning
0b0

Execution of TLBI RVAAE1IS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVAAE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TLBIRVAE1IS, bit [34]

When ARMv8.4-TLBI is implemented:

Trap execution of TLBI RVAE1IS at EL1 using AArch64 to EL2.

TLBIRVAE1ISMeaning
0b0

Execution of TLBI RVAE1IS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVAE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TLBIVAALE1IS, bit [33]

Trap execution of TLBI VAALE1IS at EL1 using AArch64 to EL2.

TLBIVAALE1ISMeaning
0b0

Execution of TLBI VAALE1IS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VAALE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

TLBIVALE1IS, bit [32]

Trap execution of TLBI VALE1IS at EL1 using AArch64 to EL2.

TLBIVALE1ISMeaning
0b0

Execution of TLBI VALE1IS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VALE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

TLBIVAAE1IS, bit [31]

Trap execution of TLBI VAAE1IS at EL1 using AArch64 to EL2.

TLBIVAAE1ISMeaning
0b0

Execution of TLBI VAAE1IS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VAAE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

TLBIASIDE1IS, bit [30]

Trap execution of TLBI ASIDE1IS at EL1 using AArch64 to EL2.

TLBIASIDE1ISMeaning
0b0

Execution of TLBI ASIDE1IS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI ASIDE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

TLBIVAE1IS, bit [29]

Trap execution of TLBI VAE1IS at EL1 using AArch64 to EL2.

TLBIVAE1ISMeaning
0b0

Execution of TLBI VAE1IS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VAE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

TLBIVMALLE1IS, bit [28]

Trap execution of TLBI VMALLE1IS at EL1 using AArch64 to EL2.

TLBIVMALLE1ISMeaning
0b0

Execution of TLBI VMALLE1IS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VMALLE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

TLBIRVAALE1OS, bit [27]

When ARMv8.4-TLBI is implemented:

Trap execution of TLBI RVAALE1OS at EL1 using AArch64 to EL2.

TLBIRVAALE1OSMeaning
0b0

Execution of TLBI RVAALE1OS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVAALE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TLBIRVALE1OS, bit [26]

When ARMv8.4-TLBI is implemented:

Trap execution of TLBI RVALE1OS at EL1 using AArch64 to EL2.

TLBIRVALE1OSMeaning
0b0

Execution of TLBI RVALE1OS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVALE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TLBIRVAAE1OS, bit [25]

When ARMv8.4-TLBI is implemented:

Trap execution of TLBI RVAAE1OS at EL1 using AArch64 to EL2.

TLBIRVAAE1OSMeaning
0b0

Execution of TLBI RVAAE1OS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVAAE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TLBIRVAE1OS, bit [24]

When ARMv8.4-TLBI is implemented:

Trap execution of TLBI RVAE1OS at EL1 using AArch64 to EL2.

TLBIRVAE1OSMeaning
0b0

Execution of TLBI RVAE1OS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI RVAE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TLBIVAALE1OS, bit [23]

When ARMv8.4-TLBI is implemented:

Trap execution of TLBI VAALE1OS at EL1 using AArch64 to EL2.

TLBIVAALE1OSMeaning
0b0

Execution of TLBI VAALE1OS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VAALE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TLBIVALE1OS, bit [22]

When ARMv8.4-TLBI is implemented:

Trap execution of TLBI VALE1OS at EL1 using AArch64 to EL2.

TLBIVALE1OSMeaning
0b0

Execution of TLBI VALE1OS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VALE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TLBIVAAE1OS, bit [21]

When ARMv8.4-TLBI is implemented:

Trap execution of TLBI VAAE1OS at EL1 using AArch64 to EL2.

TLBIVAAE1OSMeaning
0b0

Execution of TLBI VAAE1OS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VAAE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TLBIASIDE1OS, bit [20]

When ARMv8.4-TLBI is implemented:

Trap execution of TLBI ASIDE1OS at EL1 using AArch64 to EL2.

TLBIASIDE1OSMeaning
0b0

Execution of TLBI ASIDE1OS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI ASIDE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TLBIVAE1OS, bit [19]

When ARMv8.4-TLBI is implemented:

Trap execution of TLBI VAE1OS at EL1 using AArch64 to EL2.

TLBIVAE1OSMeaning
0b0

Execution of TLBI VAE1OS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VAE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

TLBIVMALLE1OS, bit [18]

When ARMv8.4-TLBI is implemented:

Trap execution of TLBI VMALLE1OS at EL1 using AArch64 to EL2.

TLBIVMALLE1OSMeaning
0b0

Execution of TLBI VMALLE1OS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of TLBI VMALLE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

ATS1E1WP, bit [17]

When ARMv8.2-ATS1E1 is implemented:

Trap execution of AT S1E1WP at EL1 using AArch64 to EL2.

ATS1E1WPMeaning
0b0

Execution of AT S1E1WP is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of AT S1E1WP at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

ATS1E1RP, bit [16]

When ARMv8.2-ATS1E1 is implemented:

Trap execution of AT S1E1RP at EL1 using AArch64 to EL2.

ATS1E1RPMeaning
0b0

Execution of AT S1E1RP is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of AT S1E1RP at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

ATS1E0W, bit [15]

Trap execution of AT S1E0W at EL1 using AArch64 to EL2.

ATS1E0WMeaning
0b0

Execution of AT S1E0W is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of AT S1E0W at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

ATS1E0R, bit [14]

Trap execution of AT S1E0R at EL1 using AArch64 to EL2.

ATS1E0RMeaning
0b0

Execution of AT S1E0R is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of AT S1E0R at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

ATS1E1W, bit [13]

Trap execution of AT S1E1W at EL1 using AArch64 to EL2.

ATS1E1WMeaning
0b0

Execution of AT S1E1W is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of AT S1E1W at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

ATS1E1R, bit [12]

Trap execution of AT S1E1R at EL1 using AArch64 to EL2.

ATS1E1RMeaning
0b0

Execution of AT S1E1R is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of AT S1E1R at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

DCZVA, bit [11]

Trap execution of multiple System instructions. Enables a trap on execution at EL1 and EL0 using AArch64 of any of the following AArch64 System instructions to EL2:

DCZVAMeaning
0b0

Execution of the System instructions listed above is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 and EL0 using AArch64 of any of the System instructions listed above is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

DCCIVAC, bit [10]

Trap execution of multiple System instructions. Enables a trap on execution at EL1 and EL0 using AArch64 of any of the following AArch64 System instructions to EL2:

DCCIVACMeaning
0b0

Execution of the System instructions listed above is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 and EL0 using AArch64 of any of the System instructions listed above is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

DCCVADP, bit [9]

When ARMv8.2-DCCVADP is implemented:

Trap execution of multiple System instructions. Enables a trap on execution at EL1 and EL0 using AArch64 of any of the following AArch64 System instructions to EL2:

DCCVADPMeaning
0b0

Execution of the System instructions listed above is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 and EL0 using AArch64 of any of the System instructions listed above is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.


Otherwise:

Reserved, RES0.

DCCVAP, bit [8]

Trap execution of multiple System instructions. Enables a trap on execution at EL1 and EL0 using AArch64 of any of the following AArch64 System instructions to EL2:

DCCVAPMeaning
0b0

Execution of the System instructions listed above is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 and EL0 using AArch64 of any of the System instructions listed above is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

DCCVAU, bit [7]

Trap execution of DC CVAU at EL1 and EL0 using AArch64 to EL2.

DCCVAUMeaning
0b0

Execution of DC CVAU is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of DC CVAU at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

DCCISW, bit [6]

Trap execution of multiple System instructions. Enables a trap on execution at EL1 using AArch64 of any of the following AArch64 System instructions to EL2:

DCCISWMeaning
0b0

Execution of the System instructions listed above is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 using AArch64 of any of the System instructions listed above is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

DCCSW, bit [5]

Trap execution of multiple System instructions. Enables a trap on execution at EL1 using AArch64 of any of the following AArch64 System instructions to EL2:

DCCSWMeaning
0b0

Execution of the System instructions listed above is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 using AArch64 of any of the System instructions listed above is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

DCISW, bit [4]

Trap execution of multiple System instructions. Enables a trap on execution at EL1 using AArch64 of any of the following AArch64 System instructions to EL2:

DCISWMeaning
0b0

Execution of the System instructions listed above is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 using AArch64 of any of the System instructions listed above is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

DCIVAC, bit [3]

Trap execution of multiple System instructions. Enables a trap on execution at EL1 using AArch64 of any of the following AArch64 System instructions to EL2:

DCIVACMeaning
0b0

Execution of the System instructions listed above is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution at EL1 using AArch64 of any of the System instructions listed above is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

ICIVAU, bit [2]

Trap execution of IC IVAU at EL1 and EL0 using AArch64 to EL2.

ICIVAUMeaning
0b0

Execution of IC IVAU is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of IC IVAU at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

ICIALLU, bit [1]

Trap execution of IC IALLU at EL1 using AArch64 to EL2.

ICIALLUMeaning
0b0

Execution of IC IALLU is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of IC IALLU at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

ICIALLUIS, bit [0]

Trap execution of IC IALLUIS at EL1 using AArch64 to EL2.

ICIALLUISMeaning
0b0

Execution of IC IALLUIS is not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state and either EL3 is not implemented or SCR_EL3.FGTEn == 1, execution of IC IALLUIS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

Accessing the HFGITR_EL2

Accesses to this register use the following encodings:

MRS <Xt>, HFGITR_EL2

op0op1CRnCRmop2
0b110b1000b00010b00010b110
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then
        return NVMem[0x1C8];
    elsif EL2Enabled() && HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FGTEn == '0' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return HFGITR_EL2;
elsif PSTATE.EL == EL3 then
    return HFGITR_EL2;
              

MSR HFGITR_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b00010b00010b110
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then
        NVMem[0x1C8] = X[t];
    elsif EL2Enabled() && HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FGTEn == '0' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        HFGITR_EL2 = X[t];
elsif PSTATE.EL == EL3 then
    HFGITR_EL2 = X[t];
              


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