PMBSR_EL1, Profiling Buffer Status/syndrome Register
The PMBSR_EL1 characteristics are:
Purpose
Provides syndrome information to software when the buffer is disabled because the management interrupt has been raised.
Configuration
This register is present only when SPE is implemented. Otherwise, direct accesses to PMBSR_EL1 are UNDEFINED.
RW fields in this register reset to architecturally UNKNOWN values.
Attributes
PMBSR_EL1 is a 64-bit register.
Field descriptions
The PMBSR_EL1 bit assignments are:
Bits [63:32]
Reserved, RES0.
EC, bits [31:26]
Exception class
Top-level description of the cause of the buffer management event
| EC | Meaning | MSS |
|---|---|---|
| 0b000000 |
Other buffer management event. All buffer management events other than those described by other defined Exception class codes. | MSS encoding for other buffer management events |
| 0b100100 |
Stage 1 Data Abort on write to Profiling Buffer. | MSS encoding for stage 1 or stage 2 Data Aborts on write to buffer |
| 0b100101 |
Stage 2 Data Abort on write to Profiling Buffer. | MSS encoding for stage 1 or stage 2 Data Aborts on write to buffer |
All other values are reserved. Reserved values might be defined in a future version of the architecture.
Writing a reserved value to this field will make the value of this field UNKNOWN. Values that are not supported act as reserved values when writing to this register.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bits [25:20]
Reserved, RES0.
DL, bit [19]
Partial record lost.
Following a buffer management event other than an asynchronous External abort, indicates whether the last record written to the Profiling Buffer is complete.
| DL | Meaning |
|---|---|
| 0b0 |
PMBPTR_EL1 points to the first byte after the last complete record written to the Profiling Buffer. |
| 0b1 |
Part of a record was lost because of a buffer management event or synchronous External abort. PMBPTR_EL1 might not point to the first byte after the last complete record written to the buffer, and so restarting collection might result in a data record stream that software cannot parse. All records prior to the last record have been written to the buffer. |
When the buffer management event was because of an asynchronous external abort, this bit is set to 1 and software must not assume that any valid data has been written to the Profiling Buffer.
This bit is RES0 if the PE never sets this bit as a result of a buffer management event caused by an asynchronous External abort.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
EA, bit [18]
External abort.
| EA | Meaning |
|---|---|
| 0b0 |
An external abort has not been asserted. |
| 0b1 |
An external abort has been asserted and detected by the Statistical Profiling Extension. |
This bit is RES0 if the PE never sets this bit as the result of an External abort.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
S, bit [17]
Service
| S | Meaning |
|---|---|
| 0b0 |
PMBIRQ is not asserted. |
| 0b1 |
PMBIRQ is asserted. All profiling data has either been written to the buffer or discarded. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
COLL, bit [16]
Collision detected.
| COLL | Meaning |
|---|---|
| 0b0 |
No collision events detected. |
| 0b1 |
At least one collision event was recorded. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
MSS, bits [15:0]
Management Event Specific Syndrome.
Contains syndrome specific to the management event.
The syndrome contents for each management event are described in the following sections.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
MSS encoding for stage 1 or stage 2 Data Aborts on write to buffer
Bits [15:6]
Reserved, RES0.
FSC, bits [5:0]
Fault status code
| FSC | Meaning | Applies when |
|---|---|---|
| 0b0000xx |
Address Size fault. Bits [1:0] encode the level. | |
| 0b0001xx |
Translation fault. Bits [1:0] encode the level. | |
| 0b0010xx |
Access Flag fault. Bits [1:0] encode the level. | |
| 0b0011xx |
Permission fault. Bits [1:0] encode the level. | |
| 0b010000 |
Synchronous External abort on write. | |
| 0b0101xx |
Synchronous External abort on translation table walk or hardware update of translation table. Bits [1:0] encode the level. | |
| 0b010001 |
Asynchronous External abort on write. | |
| 0b100001 |
Alignment fault. | |
| 0b110000 |
TLB Conflict fault. | |
| 0b110001 |
Unsupported atomic hardware update fault. | When ARMv8.1-TTHM is implemented |
All other values are reserved. Reserved values might be defined in a future version of the architecture.
Writing a reserved value to this field will make the value of this field UNKNOWN. Values that are not supported act as reserved values when writing to this register.
It is IMPLEMENTATION DEFINED whether each of the Access Flag fault, asynchronous External abort and synchronous External abort, Alignment fault, and TLB Conflict abort values can be generated by the PE. For more information see Faults and Watchpoints.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
MSS encoding for other buffer management events
Bits [15:6]
Reserved, RES0.
BSC, bits [5:0]
Buffer status code
| BSC | Meaning |
|---|---|
| 0b000000 |
Buffer not filled |
| 0b000001 |
Buffer filled |
All other values are reserved. Reserved values might be defined in a future version of the architecture.
Writing a reserved value to this field will make the value of this field UNKNOWN. Values that are not supported act as reserved values when writing to this register.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accessing the PMBSR_EL1
Accesses to this register use the following encodings:
MRS <Xt>, PMBSR_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1001 | 0b1010 | 0b011 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMBSR_EL1 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.E2PB == 'x0' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSPB != '01' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSPB != '11' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '1x1' then
return NVMem[0x820];
else
return PMBSR_EL1;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSPB != '01' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSPB != '11' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
return PMBSR_EL1;
elsif PSTATE.EL == EL3 then
return PMBSR_EL1;
MSR PMBSR_EL1, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1001 | 0b1010 | 0b011 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMBSR_EL1 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.E2PB == 'x0' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSPB != '01' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSPB != '11' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '1x1' then
NVMem[0x820] = X[t];
else
PMBSR_EL1 = X[t];
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' && MDCR_EL3.NSPB != '01' then
AArch64.SystemAccessTrap(EL3, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.NS == '1' && MDCR_EL3.NSPB != '11' then
AArch64.SystemAccessTrap(EL3, 0x18);
else
PMBSR_EL1 = X[t];
elsif PSTATE.EL == EL3 then
PMBSR_EL1 = X[t];