TLBIALLNSNH, TLB Invalidate All, Non-Secure Non-Hyp
The TLBIALLNSNH characteristics are:
Purpose
If EL2 is implemented, invalidate all cached copies of translation table entries from TLBs that are from any level of the translation table walk that would be required for stage 1 or stage 2 of the Non-secure PL1&0 translation regime, regardless of the associated VMID.
The invalidation only applies to the PE that executes this System instruction.
Configuration
This instruction is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to TLBIALLNSNH are UNKNOWN.
Attributes
TLBIALLNSNH is a 32-bit System instruction.
Field descriptions
TLBIALLNSNH ignores the value in the register specified by the instruction encoding. Software does not have to write a value to the register before issuing this instruction.
Executing the TLBIALLNSNH instruction
If this instruction is executed in a Secure privileged mode other than Monitor mode, then the behavior is CONSTRAINED UNPREDICTABLE, and one of the following behaviors must occur:
- The instruction is UNDEFINED.
- The instruction is treated as a NOP.
- The instruction executes as if it had been executed in Monitor mode.
Accesses to this instruction use the following encodings:
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b100 | 0b1000 | 0b0111 | 0b100 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T8 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T8 == '1' then
AArch32.TakeHypTrapException(0x03);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
TLBIALLNSNH();
elsif PSTATE.EL == EL3 then
if !HaveEL(EL2) then
UNDEFINED;
else
TLBIALLNSNH();