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FCSEIDR, FCSE Process ID register
The FCSEIDR characteristics are:
Purpose
Identifies whether the Fast Context Switch Extension (FCSE) is implemented.
From Armv8, the FCSE is not implemented, so this register is RAZ/WI. Software can access this register to determine that the implementation does not include the FCSE.
Configuration
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to FCSEIDR are UNKNOWN.
Attributes
FCSEIDR is a 32-bit register.
Field descriptions
The FCSEIDR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAZ/WI |
Bits [31:0]
Reserved, RAZ/WI.
Accessing the FCSEIDR
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1101 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T13 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T13 == '1' then AArch32.TakeHypTrapException(0x03); else return FCSEIDR; elsif PSTATE.EL == EL2 then return FCSEIDR; elsif PSTATE.EL == EL3 then return FCSEIDR;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b1101 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T13 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T13 == '1' then AArch32.TakeHypTrapException(0x03); else FCSEIDR = R[t]; elsif PSTATE.EL == EL2 then FCSEIDR = R[t]; elsif PSTATE.EL == EL3 then FCSEIDR = R[t];