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HAFGRTR_EL2, Hypervisor Activity Monitors Fine-Grained Read Trap Register

The HAFGRTR_EL2 characteristics are:

Purpose

Provides controls for traps of MRS reads of Activity Monitors System registers.

Configuration

This register is present only when AMUv1 is implemented and ARMv8.6-FGT is implemented. Otherwise, direct accesses to HAFGRTR_EL2 are UNDEFINED.

Attributes

HAFGRTR_EL2 is a 64-bit register.

Field descriptions

The HAFGRTR_EL2 bit assignments are:

Bits [63:50]

Reserved, RES0.

AMEVTYPER115_EL0, bit [49]

Trap MRS reads of AMEVTYPER115_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER115 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVTYPER115_EL0Meaning
0b0

MRS reads of AMEVTYPER115_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER115 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVTYPER115_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVTYPER115 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVCNTR115_EL0, bit [48]

Trap MRS reads of AMEVCNTR115_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR115 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVCNTR115_EL0Meaning
0b0

MRS reads of AMEVCNTR115_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR115 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVCNTR115_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVCNTR115 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVTYPER114_EL0, bit [47]

Trap MRS reads of AMEVTYPER114_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER114 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVTYPER114_EL0Meaning
0b0

MRS reads of AMEVTYPER114_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER114 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVTYPER114_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVTYPER114 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVCNTR114_EL0, bit [46]

Trap MRS reads of AMEVCNTR114_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR114 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVCNTR114_EL0Meaning
0b0

MRS reads of AMEVCNTR114_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR114 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVCNTR114_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVCNTR114 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVTYPER113_EL0, bit [45]

Trap MRS reads of AMEVTYPER113_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER113 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVTYPER113_EL0Meaning
0b0

MRS reads of AMEVTYPER113_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER113 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVTYPER113_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVTYPER113 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVCNTR113_EL0, bit [44]

Trap MRS reads of AMEVCNTR113_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR113 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVCNTR113_EL0Meaning
0b0

MRS reads of AMEVCNTR113_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR113 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVCNTR113_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVCNTR113 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVTYPER112_EL0, bit [43]

Trap MRS reads of AMEVTYPER112_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER112 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVTYPER112_EL0Meaning
0b0

MRS reads of AMEVTYPER112_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER112 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVTYPER112_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVTYPER112 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVCNTR112_EL0, bit [42]

Trap MRS reads of AMEVCNTR112_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR112 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVCNTR112_EL0Meaning
0b0

MRS reads of AMEVCNTR112_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR112 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVCNTR112_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVCNTR112 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVTYPER111_EL0, bit [41]

Trap MRS reads of AMEVTYPER111_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER111 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVTYPER111_EL0Meaning
0b0

MRS reads of AMEVTYPER111_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER111 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVTYPER111_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVTYPER111 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVCNTR111_EL0, bit [40]

Trap MRS reads of AMEVCNTR111_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR111 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVCNTR111_EL0Meaning
0b0

MRS reads of AMEVCNTR111_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR111 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVCNTR111_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVCNTR111 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVTYPER110_EL0, bit [39]

Trap MRS reads of AMEVTYPER110_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER110 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVTYPER110_EL0Meaning
0b0

MRS reads of AMEVTYPER110_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER110 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVTYPER110_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVTYPER110 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVCNTR110_EL0, bit [38]

Trap MRS reads of AMEVCNTR110_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR110 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVCNTR110_EL0Meaning
0b0

MRS reads of AMEVCNTR110_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR110 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVCNTR110_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVCNTR110 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVTYPER19_EL0, bit [37]

Trap MRS reads of AMEVTYPER19_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER19 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVTYPER19_EL0Meaning
0b0

MRS reads of AMEVTYPER19_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER19 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVTYPER19_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVTYPER19 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVCNTR19_EL0, bit [36]

Trap MRS reads of AMEVCNTR19_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR19 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVCNTR19_EL0Meaning
0b0

MRS reads of AMEVCNTR19_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR19 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVCNTR19_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVCNTR19 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVTYPER18_EL0, bit [35]

Trap MRS reads of AMEVTYPER18_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER18 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVTYPER18_EL0Meaning
0b0

MRS reads of AMEVTYPER18_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER18 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVTYPER18_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVTYPER18 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVCNTR18_EL0, bit [34]

Trap MRS reads of AMEVCNTR18_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR18 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVCNTR18_EL0Meaning
0b0

MRS reads of AMEVCNTR18_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR18 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVCNTR18_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVCNTR18 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVTYPER17_EL0, bit [33]

Trap MRS reads of AMEVTYPER17_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER17 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVTYPER17_EL0Meaning
0b0

MRS reads of AMEVTYPER17_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER17 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVTYPER17_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVTYPER17 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVCNTR17_EL0, bit [32]

Trap MRS reads of AMEVCNTR17_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR17 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVCNTR17_EL0Meaning
0b0

MRS reads of AMEVCNTR17_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR17 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVCNTR17_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVCNTR17 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVTYPER16_EL0, bit [31]

Trap MRS reads of AMEVTYPER16_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER16 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVTYPER16_EL0Meaning
0b0

MRS reads of AMEVTYPER16_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER16 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVTYPER16_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVTYPER16 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVCNTR16_EL0, bit [30]

Trap MRS reads of AMEVCNTR16_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR16 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVCNTR16_EL0Meaning
0b0

MRS reads of AMEVCNTR16_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR16 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVCNTR16_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVCNTR16 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVTYPER15_EL0, bit [29]

Trap MRS reads of AMEVTYPER15_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER15 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVTYPER15_EL0Meaning
0b0

MRS reads of AMEVTYPER15_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER15 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVTYPER15_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVTYPER15 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVCNTR15_EL0, bit [28]

Trap MRS reads of AMEVCNTR15_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR15 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVCNTR15_EL0Meaning
0b0

MRS reads of AMEVCNTR15_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR15 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVCNTR15_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVCNTR15 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVTYPER14_EL0, bit [27]

Trap MRS reads of AMEVTYPER14_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER14 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVTYPER14_EL0Meaning
0b0

MRS reads of AMEVTYPER14_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER14 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVTYPER14_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVTYPER14 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVCNTR14_EL0, bit [26]

Trap MRS reads of AMEVCNTR14_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR14 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVCNTR14_EL0Meaning
0b0

MRS reads of AMEVCNTR14_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR14 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVCNTR14_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVCNTR14 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVTYPER13_EL0, bit [25]

Trap MRS reads of AMEVTYPER13_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER13 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVTYPER13_EL0Meaning
0b0

MRS reads of AMEVTYPER13_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER13 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVTYPER13_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVTYPER13 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVCNTR13_EL0, bit [24]

Trap MRS reads of AMEVCNTR13_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR13 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVCNTR13_EL0Meaning
0b0

MRS reads of AMEVCNTR13_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR13 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVCNTR13_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVCNTR13 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVTYPER12_EL0, bit [23]

Trap MRS reads of AMEVTYPER12_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER12 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVTYPER12_EL0Meaning
0b0

MRS reads of AMEVTYPER12_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER12 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVTYPER12_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVTYPER12 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVCNTR12_EL0, bit [22]

Trap MRS reads of AMEVCNTR12_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR12 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVCNTR12_EL0Meaning
0b0

MRS reads of AMEVCNTR12_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR12 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVCNTR12_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVCNTR12 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVTYPER11_EL0, bit [21]

Trap MRS reads of AMEVTYPER11_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER11 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVTYPER11_EL0Meaning
0b0

MRS reads of AMEVTYPER11_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER11 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVTYPER11_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVTYPER11 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVCNTR11_EL0, bit [20]

Trap MRS reads of AMEVCNTR11_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR11 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVCNTR11_EL0Meaning
0b0

MRS reads of AMEVCNTR11_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR11 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVCNTR11_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVCNTR11 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVTYPER10_EL0, bit [19]

Trap MRS reads of AMEVTYPER10_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER10 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVTYPER10_EL0Meaning
0b0

MRS reads of AMEVTYPER10_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER10 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVTYPER10_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVTYPER10 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMEVCNTR10_EL0, bit [18]

Trap MRS reads of AMEVCNTR10_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR10 at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVCNTR10_EL0Meaning
0b0

MRS reads of AMEVCNTR10_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR10 at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVCNTR10_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVCNTR10 at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMCNTEN1, bit [17]

Trap MRS reads and MRC reads of multiple System registers.

Enables a trap to EL2 the following operations:

AMCNTEN1Meaning
0b0

The operations listed above are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads at EL1 and EL0 using AArch64 of AMCNTENCLR1_EL0 and AMCNTENSET1_EL0 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads at EL0 using AArch32 of AMCNTENCLR1 and AMCNTENSET1 are trapped to EL2 and reported with EC syndrome value 0x03, unless the read generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

Bits [16:5]

Reserved, RES0.

AMEVCNTR0<x>_EL0, bit [x+1], for x = 0 to 3

Trap MRS reads of AMEVCNTR0<x>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR0<x> at EL0 using AArch32 when EL1 is using AArch64 to EL2.

AMEVCNTR0<x>_EL0Meaning
0b0

MRS reads of AMEVCNTR0<x>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR0<x> at EL0 using AArch32 are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads of AMEVCNTR0<x>_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads of AMEVCNTR0<x> at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03.

In a system where the PE resets into EL2, this field resets to 0.

AMCNTEN0, bit [0]

Trap MRS reads and MRC reads of multiple System registers.

Enables a trap to EL2 the following operations:

AMCNTEN0Meaning
0b0

The operations listed above are not affected by this bit.

0b1

If EL2 is implemented and enabled in the current Security state, HCR_EL2.{E2H,TGE} != {1,1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception:

  • MRS reads at EL1 and EL0 using AArch64 of AMCNTENCLR0_EL0 and AMCNTENSET0_EL0 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MRC reads at EL0 using AArch32 of AMCNTENCLR0 and AMCNTENSET0 are trapped to EL2 and reported with EC syndrome value 0x03, unless the read generates a higher priority exception.

In a system where the PE resets into EL2, this field resets to 0.

Accessing the HAFGRTR_EL2

Accesses to this register use the following encodings:

MRS <Xt>, HAFGRTR_EL2

op0op1CRnCRmop2
0b110b1000b00110b00010b110
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then
        return NVMem[0x1E8];
    elsif EL2Enabled() && HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FGTEn == '0' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        return HAFGRTR_EL2;
elsif PSTATE.EL == EL3 then
    return HAFGRTR_EL2;
              

MSR HAFGRTR_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b00110b00010b110
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then
        NVMem[0x1E8] = X[t];
    elsif EL2Enabled() && HCR_EL2.NV == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    else
        UNDEFINED;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FGTEn == '0' then
        AArch64.SystemAccessTrap(EL3, 0x18);
    else
        HAFGRTR_EL2 = X[t];
elsif PSTATE.EL == EL3 then
    HAFGRTR_EL2 = X[t];