AMPIDR0, Activity Monitors Peripheral Identification Register 0
The AMPIDR0 characteristics are:
Provides information to identify an activity monitors component.
For more information, see About the Peripheral identification scheme in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
The power domain of AMPIDR0 is IMPLEMENTATION DEFINED.
Implementation of this register is OPTIONAL.
This register is present only when AMUv1 is implemented. Otherwise, direct accesses to AMPIDR0 are RES0.
AMPIDR0 is a 32-bit register.
The AMPIDR0 bit assignments are:
PART_0, bits [7:0]
Part number, least significant byte.
The value of this field is IMPLEMENTATION DEFINED.
Accessing the AMPIDR0
AMPIDR0 can be accessed through the memory-mapped interfaces:
Accesses on this interface are RO.