CNTSR, Counter Status Register
The CNTSR characteristics are:
Provides counter frequency status information.
The power domain of CNTSR is IMPLEMENTATION DEFINED.
For more information see 'Power and reset domains for the system level implementation of the Generic Timer' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
CNTSR is a 32-bit register.
The CNTSR bit assignments are:
FCACK, bits [31:8]
Frequency change acknowledge. Indicates the currently selected entry in the Frequency modes table, see 'The Frequency modes table' in Chapter I1 of the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.
This field resets to 0.
DBGH, bit 
Indicates whether the counter is halted because the Halt-on-debug signal is asserted:
Counter is not halted.
Counter is halted.
This field resets to an architecturally UNKNOWN value.
Accessing the CNTSR
In a system that supports Secure and Non-secure memory maps the CNTControlBase frame, that includes this register, is implemented only in the Secure memory map.
CNTSR can be accessed through the memory-mapped interfaces:
Accesses on this interface are RO.