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CTIPIDR2, CTI Peripheral Identification Register 2

The CTIPIDR2 characteristics are:


Provides information to identify a CTI component.

For more information see 'About the Peripheral identification scheme' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H8 (About the External Debug Registers).


CTIPIDR2 is in the Debug power domain.

Implementation of this register is OPTIONAL.

This register is required for CoreSight compliance.


CTIPIDR2 is a 32-bit register.

Field descriptions

The CTIPIDR2 bit assignments are:


Bits [31:8]

Reserved, RES0.

REVISION, bits [7:4]

Part major revision. Parts can also use this field to extend Part number to 16-bits.

JEDEC, bit [3]

RAO. Indicates a JEP106 identity code is used.

DES_1, bits [2:0]

Designer, most significant bits of JEP106 ID code. For Arm Limited, this field is 0b011.

Accessing the CTIPIDR2

CTIPIDR2 can be accessed through the external debug interface:


Accesses on this interface are RO.