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CTIPIDR4, CTI Peripheral Identification Register 4

The CTIPIDR4 characteristics are:


Provides information to identify a CTI component.

For more information see 'About the Peripheral identification scheme' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H8 (About the External Debug Registers).


CTIPIDR4 is in the Debug power domain.

Implementation of this register is OPTIONAL.

This register is required for CoreSight compliance.


CTIPIDR4 is a 32-bit register.

Field descriptions

The CTIPIDR4 bit assignments are:


Bits [31:8]

Reserved, RES0.

SIZE, bits [7:4]

Size of the component. RAZ. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers.

DES_2, bits [3:0]

Designer, JEP106 continuation code, least significant nibble. For Arm Limited, this field is 0b0100.

Accessing the CTIPIDR4

CTIPIDR4 can be accessed through the external debug interface:


Accesses on this interface are RO.