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EDECR, External Debug Execution Control Register

The EDECR characteristics are:

Purpose

Controls Halting debug events.

Configuration

If ARMv8.3-DoPD is implemented, this register is in the Core power domain.

If ARMv8.3-DoPD is not implemented, this register is in the Debug power domain.

Attributes

EDECR is a 32-bit register.

Field descriptions

The EDECR bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0SSRCEOSUCE

Bits [31:3]

Reserved, RES0.

SS, bit [2]

Halting step enable. Possible values of this field are:

SSMeaning
0b0

Halting step debug event disabled.

0b1

Halting step debug event enabled.

If the value of EDECR.SS is changed when the PE is in Non-debug state, behavior is CONSTRAINED UNPREDICTABLE as described in 'Changing the value of EDECR.SS when not in Debug state' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile.

The following resets apply:

  • On a Cold reset, this field resets to:

    • If ARMv8.3-DoPD is implemented, 0.
  • On an External debug reset, this field resets to:

    • If ARMv8.3-DoPD is not implemented, 0.
  • On a Warm reset, this field resets to:

    • If ARMv8.3-DoPD is implemented, an unchanged value.

RCE, bit [1]

When ARMv8.3-DoPD is not implemented:

Reset Catch Enable.

RCEMeaning
0b0

Reset Catch debug event disabled.

0b1

Reset Catch debug event enabled.

The following resets apply:

  • On an External debug reset, this field resets to 0.

  • On a Warm reset, the value of this field is unchanged.


Otherwise:

Reserved, RES0.

OSUCE, bit [0]

When ARMv8.3-DoPD is not implemented:

OS Unlock Catch Enable.

OSUCEMeaning
0b0

OS Unlock Catch debug event disabled.

0b1

OS Unlock Catch debug event enabled.

The following resets apply:

  • On an External debug reset, this field resets to 0.

  • On a Warm reset, the value of this field is unchanged.


Otherwise:

Reserved, RES0.

Accessing the EDECR

EDECR can be accessed through the external debug interface:

ComponentOffsetInstance
Debug0x024EDECR

This interface is accessible as follows:

  • When (ARMv8.3-DoPD is not implemented or IsCorePowered()) and SoftwareLockStatus() accesses to this register are RO.
  • When (ARMv8.3-DoPD is not implemented or IsCorePowered()) and !SoftwareLockStatus() accesses to this register are RW.
  • Otherwise accesses to this register generate an error response.