You copied the Doc URL to your clipboard.

ERRCRICR0, Critical Error Interrupt Configuration Register 0

The ERRCRICR0 characteristics are:

Purpose

Interrupt configuration register.

Configuration

External register ERRCRICR0 is architecturally mapped to External register ERRIRQCR4.

This register is present only when ARMv8.4-RAS is implemented. Otherwise, direct accesses to ERRCRICR0 are RES0.

Present only if interrupt configuration registers use the recommended format. Otherwise, this register is RES0.

Attributes

ERRCRICR0 is a 64-bit register.

Field descriptions

The ERRCRICR0 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0ADDR
ADDRRES0
313029282726252423222120191817161514131211109876543210

Bits [63:56]

Reserved, RES0.

ADDR, bits [55:2]

Message Signaled Interrupt address.

Specifies the address that the component writes to when signaling an interrupt.

The size of a physical address is IMPLEMENTATION DEFINED. Unimplemented high-order physical address bits are RES0.

The following resets apply:

  • On an Error recovery reset, this field resets to an architecturally UNKNOWN value.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

Bits [1:0]

Reserved, RES0.

Accessing the ERRCRICR0

ERRCRICR0 can be accessed through the memory-mapped interfaces:

ComponentOffsetInstance
RAS0xEA0ERRCRICR0

Accesses on this interface are RW.