ERRIRQCR<n>, Generic Error Interrupt Configuration Register, n = 0 - 15

The ERRIRQCR<n> characteristics are:

Purpose

The ERRIRQCR<n> registers are IMPLEMENTATION DEFINED interrupt configuration registers.

The architecture provides a recommended format for the ERRIRQCR<n> registers. The registers provided by the recommended layout are:

• ERRFHICR0, ERRFHICR1, and ERRFHICR2, the fault-handling interrupt configuration registers. ERRFHICR<m> maps to ERRIRQCR0 and ERRIRQCR1.

• ERRERICR0, ERRERICR1, and ERRERICR2, the error recovery interrupt configuration registers. ERRERICR<m> maps to ERRIRQCR2 and ERRIRQCR3.

• If ARMv8.4-RAS is implemented, ERRCRICR0, ERRCRICR1, and ERRCRICR2, the critical error interrupt configuration registers. ERRFHICR<m> maps to ERRIRQCR4 and ERRIRQCR5.

• ERRIRQSR, the error interrupt status register. ERRIRQSR maps to ERRIRQCR15.

This register describes the generic IMPLEMENTATION DEFINED format of the interrupt configuration registers, when the recommended layout is not used.

Configuration

This register is present only when the interrupt configuration registers are implemented. Otherwise, direct accesses to ERRIRQCR<n> are RES0.

Attributes

ERRIRQCR<n> is a 64-bit register.

Field descriptions

The ERRIRQCR<n> bit assignments are:

IMPLEMENTATION DEFINED, bits [63:0]

IMPLEMENTATION DEFINED.

IMPLEMENTATION DEFINED controls. The content of these registers is IMPLEMENTATION DEFINED.

Accessing the ERRIRQCR<n>

ERRIRQCR<n> can be accessed through the memory-mapped interfaces:

Accesses on this interface are RW.