ERR<n>MISC3, Error Record Miscellaneous Register 3, n = 0 - 65534
The ERR<n>MISC3 characteristics are:
IMPLEMENTATION DEFINED error syndrome register. The miscellaneous syndrome registers might contain:
- Information to identify the FRU in which the error was detected, and might contain enough information to locate the error within that FRU.
- A Corrected error counter or counters.
- Other state information not present in the corresponding status and address registers.
If the node that owns error record n supports the RAS Timestamp Extension (ERR<q>FR.TS != 0b00), then ERR<n>MISC3 contains the timestamp value for error record n when the error was detected. Otherwise the contents of ERR<n>MISC3 are IMPLEMENTATION DEFINED.
This register is present only when error record <n> is implemented. Otherwise, direct accesses to ERR<n>MISC3 are RES0.
ERR<q>FR describes the features implemented by the node that owns error record <n>. <q> is the index of the first error record owned by the same node as error record <n>. If the node owns a single record, then q = n.
For IMPLEMENTATION DEFINED fields in ERR<n>MISC3, writing zero must always be supported to return the error record to an initial quiescent state.
In particular, if any IMPLEMENTATION DEFINED syndrome fields might generate a Fault Handling or Error Recovery Interrupt request, writing zero is sufficient to deactivate the Interrupt request.
Fields that are read-only, non-zero, and ignore writes are compliant with this requirement.
If RAS System Architecture v1.1 is not implemented, Arm recommendeds that ERR<n>MISC3 does not require zeroing to return the record to a quiescent state.
Arm recommends that any IMPLEMENTATION DEFINED syndrome fields that can generate a Fault Handling, Error Recovery, Critical, or IMPLEMENTATION DEFINED, interrupt request are disabled at Cold reset and are enabled by software writing an IMPLEMENTATION DEFINED non-zero value to an IMPLEMENTATION DEFINED field in ERR<q>CTRL.
It is IMPLEMENTATION DEFINED whether ERR<n>MISC3 is present if RAS System Architecture v1.1 is not implemented. ERR<n>MISC3 is RES0 if not present.
ERR<n>MISC3 is a 64-bit register.
The ERR<n>MISC3 bit assignments are:
When ERR<q>FR.TS != 0b00:
TS, bits [63:0]
Timestamp. Timestamp value recorded when the error was detected. Valid only if ERR<n>STATUS.V == 0b1.
The following resets apply:
On an Error recovery reset, the value of this field is unchanged.
On a Cold reset, this field resets to an architecturally UNKNOWN value.
Access to this field is RO or RW.
When ERR<q>FR.TS == 0b00:
IMPLEMENTATION DEFINED, bits [63:0]
IMPLEMENTATION DEFINED syndrome.
Accessing the ERR<n>MISC3
Reads from ERR<n>MISC3 return an IMPLEMENTATION DEFINED value and writes have IMPLEMENTATION DEFINED behavior.
Arm recommends that miscellaneous syndrome for multiple errors, such as a corrected error counter, is read/write.
When ERR<n>STATUS.MV == 0b1, the miscellaneous syndrome specific to the most recently recorded error should ignore writes.
These recommendations allow a counter to be reset in the presence of a persistent error, while preventing specific information, such as that identifying a FRU, from being lost if an error is detected while the previous error is being logged.
ERR<n>MISC3 can be accessed through the memory-mapped interfaces:
|RAS||0x038 + 64n||ERR<n>MISC3|
Accesses on this interface are RW.