GICC_BPR, CPU Interface Binary Point Register
The GICC_BPR characteristics are:
Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
In systems that support two Security states:
- This register is Banked.
- The Secure instance of this register determines Group 0 interrupt preemption.
- The Non-secure instance of this register determines Group 1 interrupt preemption.
In systems that support only one Security state, when GICC_CTLR.CBPR == 0, this register determines only Group 0 interrupt preemption.
When GICC_CTLR.CBPR == 1, this register determines interrupt preemption for both Group 0 and Group 1 interrupts.
GICC_BPR is a 32-bit register.
The GICC_BPR bit assignments are:
Binary_Point, bits [2:0]
Controls how the 8-bit interrupt priority field is split into a group priority field, that determines interrupt preemption, and a subpriority field. The following list describes how this field determines the interrupt priority bits assigned to the group priority field:
- Priority grouping for Group 1 interrupts when CBPR==0, for the processing of Group 1 interrupts in a GIC implementation that supports interrupt grouping, when GICC_CTLR.CBPR == 0.
- Priority grouping for Group 0 interrupts, or Group 1 interrupts when CBPR==1, for all other cases.
This field resets to an architecturally UNKNOWN value.
Accessing the GICC_BPR
This register is used only when System register access is not enabled. When System register access is enabled this register is RAZ/WI, and the System registers ICC_BPR0_EL1 and ICC_BPR1_EL1 provide equivalent functionality.
GICC_BPR can be accessed through the memory-mapped interfaces:
|GIC CPU interface||0x0008||GICC_BPR|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0b0 accesses to this register are RW.
- When IsAccessSecure() accesses to this register are RW.
- When !IsAccessSecure() accesses to this register are RW.