GICC_NSAPR<n>, CPU Interface Non-secure Active Priorities Registers, n = 0 - 3
The GICC_NSAPR<n> characteristics are:
Provides information about Group 1 interrupt active priorities.
The contents of these registers are IMPLEMENTATION DEFINED with the one architectural requirement that the value 0x00000000 is consistent with no interrupts being active.
When GICD_CTLR.DS==0, these registers are RAZ/WI to Non-secure accesses.
GICC_NSAPR1 is only implemented in implementations that support 6 or more bits of priority. GICC_NSAPR2 and GICC_NSAPR3 are only implemented in implementations that support 7 bits of priority.
GICC_NSAPR<n> is a 32-bit register.
The GICC_NSAPR<n> bit assignments are:
IMPLEMENTATION DEFINED, bits [31:0]
This field resets to 0.
Accessing the GICC_NSAPR<n>
GICC_NSAPR<n> can be accessed through the memory-mapped interfaces:
|GIC CPU interface||0x00E0 + 4n||GICC_NSAPR<n>|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0b0 accesses to this register are RW.
- When IsAccessSecure() accesses to this register are RW.
- When !IsAccessSecure() accesses to this register are RW.