GICC_PMR, CPU Interface Priority Mask Register
The GICC_PMR characteristics are:
This register provides an interrupt priority filter. Only interrupts with a higher priority than the value in this register are signaled to the PE.
Higher interrupt priority corresponds to a lower value of the Priority field.
This register is available in all configurations of the GIC. If the GIC implementation supports two Security states this register is Common.
GICC_PMR is a 32-bit register.
The GICC_PMR bit assignments are:
Priority, bits [7:0]
The priority mask level for the CPU interface. If the priority of the interrupt is higher than the value indicated by this field, the interface signals the interrupt to the PE.
If the GIC implementation supports fewer than 256 priority levels some bits might be RAZ/WI, as follows:
- For 128 supported levels, bit  = 0b0.
- For 64 supported levels, bits [1:0] = 0b00.
- For 32 supported levels, bits [2:0] = 0b000.
- For 16 supported levels, bits [3:0] = 0b0000.
See Interrupt prioritization for more information.
This field resets to an architecturally UNKNOWN value.
Accessing the GICC_PMR
If the GIC implementation supports two Security states:
- Non-secure accesses to this register can only read or write values corresponding to the lower half of the priority range.
- If a Secure write has programmed the register with a value that corresponds to a value in the upper half of the priority range then:
- Any Non-secure read of the register returns 0x00, regardless of the value held in the register.
- Non-secure writes are ignored.
See 'Priority control of Secure and Non-secure interrupts' in the GICv3 Architecture Specification for more information.
GICC_PMR can be accessed through the memory-mapped interfaces:
|GIC CPU interface||0x0004||GICC_PMR|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0b0 accesses to this register are RW.
- When IsAccessSecure() accesses to this register are RW.
- When !IsAccessSecure() accesses to this register are RW.