GICD_IGRPMODR<n>E, Interrupt Group Modifier Registers (extended SPI range), n = 0 - 31
The GICD_IGRPMODR<n>E characteristics are:
Purpose
When GICD_CTLR.DS==0, this register together with the GICD_IGROUPR<n>E registers, controls whether the corresponding interrupt is in:
- Secure Group 0.
- Non-secure Group 1.
- When System register access is enabled, Secure Group 1.
Configuration
This register is present only when GICv3.1 is implemented. Otherwise, direct accesses to GICD_IGRPMODR<n>E are RES0.
GICD_IGRPMODR<n>E resets to 0x00000000.
When GICD_TYPER.ESPI==0, these registers are RES0.
When GICD_TYPER.ESPI==1:
- The number of implemented GICD_IGRPMODR<n>E registers is (GICD_TYPER.ESPI_range+1). Registers are numbered from 0.
- When GICD_CTLR.DS==0, this register is Secure.
Attributes
GICD_IGRPMODR<n>E is a 32-bit register.
Field descriptions
The GICD_IGRPMODR<n>E bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Group_modifier_bit<x>, bit [x], for x = 0 to 31 | |||||||||||||||||||||||||||||||
Group_modifier_bit<x>, bit [x], for x = 0 to 31
Group modifier bit. In implementations where affinity routing is enabled for the Security state of an interrupt, the bit that corresponds to the interrupt is concatenated with the equivalent bit in GICD_IGROUPR<n>E to form a 2-bit field that defines an interrupt group:
| Group modifier bit | Group status bit | Definition | Short name |
|---|---|---|---|
| 0b0 | 0b0 | Secure Group 0 | G0S |
| 0b0 | 0b1 | Non-secure Group 1 | G1NS |
| 0b1 | 0b0 | Secure Group 1 | G1S |
| 0b1 | 0b1 | Reserved, treated as Non-secure Group 1 | - |
This field resets to 0.
For INTID m, when DIV and MOD are the integer division and modulo operations:
- The corresponding GICD_IGRPMODR<n>E number, n, is given by n = (m-4096) DIV 32.
- The offset of the required GICD_IGRPMODR<n>E is (0x3400 + (4*n)).
- The bit number of the required group modifier bit in this register is (m-4096) MOD 32.
Accessing the GICD_IGRPMODR<n>E
When affinity routing is not enabled for the Security state of an interrupt in GICD_IGRPMODR<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, bits corresponding to Secure SPIs are RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
GICD_IGRPMODR<n>E can be accessed through the memory-mapped interfaces:
| Component | Offset | Instance |
|---|---|---|
| GIC Distributor | 0x3400 + 4n | GICD_IGRPMODR<n>E |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0b0 accesses to this register are RW.
- When IsAccessSecure() accesses to this register are RW.
- When !IsAccessSecure() accesses to this register are RW.