GICH_EISR, End Interrupt Status Register
The GICH_EISR characteristics are:
Indicates which List registers have outstanding EOI maintenance interrupts.
This register is available when the GIC implementation supports interrupt virtualization.
GICH_EISR is a 32-bit register.
The GICH_EISR bit assignments are:
Status<n>, bit [n], for n = 0 to 15
EOI maintenance interrupt status for List register <n>:
GICH_LR<n> does not have an EOI maintenance interrupt.
GICH_LR<n> has an EOI maintenance interrupt that has not been handled.
For any GICH_LR<n> register, the corresponding status bit is set to 1 if all of the following are true:
This field resets to an architecturally UNKNOWN value.
Accessing the GICH_EISR
This register is used only when System register access is not enabled. When System register access is enabled:
- For AArch32 implementations, ICH_EISR provides equivalent functionality.
- For AArch64 implementations, ICH_EISR_EL2 provides equivalent functionality.
Bits corresponding to unimplemented List registers are RAZ.
GICH_EISR can be accessed through the memory-mapped interfaces:
|GIC Virtual interface control||0x0020||GICH_EISR|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0b0 accesses to this register are RO.
- When IsAccessSecure() accesses to this register are RO.
- When !IsAccessSecure() accesses to this register are RO.