GICR_CLRLPIR, Clear LPI Pending Register
The GICR_CLRLPIR characteristics are:
Purpose
Clears the pending state of the specified LPI.
Configuration
This register is present only when GICv4.1 is implemented. Otherwise, direct accesses to GICR_CLRLPIR are RES0.
A copy of this register is provided for each Redistributor.
Attributes
GICR_CLRLPIR is a 64-bit register.
Field descriptions
The GICR_CLRLPIR bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| pINTID | |||||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:32]
Reserved, RES0.
pINTID, bits [31:0]
The INTID of the physical LPI.
The size of this field is IMPLEMENTATION DEFINED, and is specified by the GICD_TYPER.IDbits field. Unimplemented bits are RES0.
Accessing the GICR_CLRLPIR
When written with a 32-bit write the data is zero-extended to 64 bits.
This register is mandatory in an implementation that supports LPIs and does not include an ITS. The functionality of this register is IMPLEMENTATION DEFINED in an implementation that does include an ITS.
Writes to this register have no effect if any of the following apply:
- GICR_CTLR.EnableLPIs == 0.
- The pINTID value specifies an unimplemented LPI.
- The pINTID value specifies an LPI that is not pending.
GICR_CLRLPIR can be accessed through the memory-mapped interfaces:
| Component | Frame | Offset | Instance |
|---|---|---|---|
| GIC Redistributor | RD_base | 0x0048 | GICR_CLRLPIR |
This interface is accessible as follows:
- When GICD_CTLR.DS == 0b0 accesses to this register are WO.
- When IsAccessSecure() accesses to this register are WO.
- When !IsAccessSecure() accesses to this register are WO.