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GICR_VSGIR, Redistributor virtual SGI pending state request register

The GICR_VSGIR characteristics are:


Requests the pending state of virtual SGIs for a specified vPE.


This register is present only when GICv4.1 is implemented. Otherwise, direct accesses to GICR_VSGIR are RES0.

A copy of this register is provided for each Redistributor.


GICR_VSGIR is a 32-bit register.

Field descriptions

The GICR_VSGIR bit assignments are:


Bits [31:16]

Reserved, RES0.

vPEID, bits [15:0]

ID of target vPE

Writing this field is CONSTRAINED UNPREDICTABLE when GICR_VSGIPENDR.Busy == 1, with either the write ignored or a new query started.

Writing a value greater than the configured vPEID width behaviur is CONSTRAINED UNPREDICTABLE:

  • GICR_VPENDBASER.vPEID is treated as having an UNKNOWN valid value for all purposes other than a direct read of the register.

  • GICR_VPENDBASER.Valid is treated as being set to 0 for all purposes other than a direct read of the register.

The size of this field is IMPLEMENTATION DEFINED, and is specified by the GICD_TYPER2.VIL and GICD_TYPER2.VID fields. Unimplemented bits are RES0.

Accessing the GICR_VSGIR

64-bit access only.

GICR_VSGIR can be accessed through the memory-mapped interfaces:

GIC RedistributorVLPI_base0x0080GICR_VSGIR

This interface is accessible as follows:

  • When GICD_CTLR.DS == 0b0 accesses to this register are WO.
  • When IsAccessSecure() accesses to this register are WO.
  • When !IsAccessSecure() accesses to this register are WO.