MPAMF_CPOR_IDR, MPAM Features Cache Portion Partitioning ID register
The MPAMF_CPOR_IDR characteristics are:
Purpose
Indicates the number of bits in MPAMCFG_CPBM for this MSC. MPAMF_CPOR_IDR_s indicates the number of bits in the Secure instance of MPAMCFG_CPBM. MPAMF_CPOR_IDR_ns indicates the number of bits in the Non-secure instance of MPAMCFG_CPBM.
Configuration
The power domain of MPAMF_CPOR_IDR is IMPLEMENTATION DEFINED.
This register is present only when MPAMF_IDR.HAS_CPOR_PART == 1. Otherwise, direct accesses to MPAMF_CPOR_IDR are RES0.
Attributes
MPAMF_CPOR_IDR is a 32-bit register.
Field descriptions
The MPAMF_CPOR_IDR bit assignments are:
Bits [31:16]
Reserved, RES0.
CPBM_WD, bits [15:0]
Number of bits in the cache portion partitioning bit map of this device. See MPAMCFG_CPBM.
This field must contain a value from 1 to 32768, inclusive. Values greater than 32 require a group of 32-bit registers to access the CPBM, up to 1024 if CPBM_WD is the largest value.
Accessing the MPAMF_CPOR_IDR
This register is within the MPAM feature page memory frames. In a system that supports Secure and Non-secure memory maps, there must be both Secure and Non-secure MPAM feature pages.
MPAMF_CPOR_IDR is read-only.
MPAMF_CPOR_IDR must be readable from the Non-secure and Secure MPAM feature pages.
MPAMF_CPOR_IDR is permitted to have the same contents when read from either the Secure and Non-secure MPAM feature pages unless the register contents is different for Secure and Non-secure versions, when there must be separate registers in the Secure (MPAMF_CPOR_IDR_s) and Non-secure (MPAMF_CPOR_IDR_ns) MPAM feature pages.
MPAMF_CPOR_IDR can be accessed through the memory-mapped interfaces:
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_s | 0x0030 | MPAMF_CPOR_IDR_s |
Accesses on this interface are RO.
Component | Frame | Offset | Instance |
---|---|---|---|
MPAM | MPAMF_BASE_ns | 0x0030 | MPAMF_CPOR_IDR_ns |
Accesses on this interface are RO.