MPAMF_MBW_IDR, MPAM Memory Bandwidth Partitioning Identification Register
The MPAMF_MBW_IDR characteristics are:
Purpose
Indicates which MPAM bandwidth partitioning features are present on this MSC. MPAMF_MBW_IDR_s indicates bandwidth partitioning features accessed from the Secure MPAM feature page. MPAMF_MBW_IDR_ns indicates bandwidth partitioning features accessed from the Non-secure MPAM feature page.
Configuration
The power domain of MPAMF_MBW_IDR is IMPLEMENTATION DEFINED.
This register is present only when MPAMF_IDR.HAS_MBW_PART == 1. Otherwise, direct accesses to MPAMF_MBW_IDR are RES0.
Attributes
MPAMF_MBW_IDR is a 32-bit register.
Field descriptions
The MPAMF_MBW_IDR bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | BWPBM_WD | RES0 | WINDWR | HAS_PROP | HAS_PBM | HAS_MAX | HAS_MIN | RES0 | BWA_WD | ||||||||||||||||||||||
Bits [31:29]
Reserved, RES0.
BWPBM_WD, bits [28:16]
Bandwidth portion bitmap width.
The number of bandwidth portion bits in MPAMCFG_MBW_PBM.BWPBM.
This field must contain a value from 1 to 4096, inclusive. Values greater than 32 require a group of 32-bit registers to access the BWPBM, up to 128 if BWPBM_WD is the largest value.
Bit [15]
Reserved, RES0.
WINDWR, bit [14]
Indicates the bandwidth accounting period register is writable.
| WINDWR | Meaning |
|---|---|
| 0b0 |
The bandwidth accounting period is readable from MPAMCFG_MBW_WINWD which might be fixed or vary due to clock rate reconfiguration of the memory channel or memory controller. |
| 0b1 |
The bandwidth accounting width is readable and writable per partition in MPAMCFG_MBW_WINWD. |
HAS_PROP, bit [13]
Indicates that this MSC implements proportional stride bandwidth partitioning and the MPAMCFG_MBW_PROP register.
| HAS_PROP | Meaning |
|---|---|
| 0b0 |
There is no memory bandwidth proportional stride control and no MPAMCFG_MBW_PROP register. |
| 0b1 |
The MPAMCFG_MBW_PROP register exists and the proportional stride memory bandwidth allocation scheme is supported. |
HAS_PBM, bit [12]
Indicates that this MSC implements bandwidth portion partitioning and the MPAMCFG_MBW_PBM register.
| HAS_PBM | Meaning |
|---|---|
| 0b0 |
There is no memory bandwidth portion control and no MPAMCFG_MBW_PBM register. |
| 0b1 |
The MPAMCFG_MBW_PBM register exists and the memory bandwidth portion allocation scheme exists. |
HAS_MAX, bit [11]
Indicates that this MSC implements maximum bandwidth partitioning and the MPAMCFG_MBW_MAX register.
| HAS_MAX | Meaning |
|---|---|
| 0b0 |
There is no maximum memory bandwidth control and no MPAMCFG_MBW_MAX register. |
| 0b1 |
The MPAMCFG_MBW_MAX register exists and the maximum memory bandwidth allocation scheme is supported. |
HAS_MIN, bit [10]
Indicates that this MSC implements minimum bandwidth partitioning.
| HAS_MIN | Meaning |
|---|---|
| 0b0 |
There is no minimum memory bandwidth control and no MPAMCFG_MBW_MIN register. |
| 0b1 |
The MPAMCFG_MBW_MIN register exists and the minimum memory bandwidth allocation scheme is supported. |
Bits [9:6]
Reserved, RES0.
BWA_WD, bits [5:0]
Number of implemented bits in the bandwidth allocation fields: MIN, MAX and STRIDE. See MPAMCFG_MBW_MIN, MPAMCFG_MBW_MAX and MPAMCFG_MBW_PROP.
This field must have a value from 1 to 16, inclusive.
Accessing the MPAMF_MBW_IDR
This register is within the MPAM feature page memory frames. In a system that supports Secure and Non-secure memory maps, there must be both Secure and Non-secure MPAM feature pages.
MPAMF_MBW_IDR is read-only.
MPAMF_MBW_IDR must be readable from the Non-secure and Secure MPAM feature pages.
MPAMF_MBW_IDR is permitted to have the same contents when read from either the Secure and Non-secure MPAM feature pages unless the register contents is different for Secure and Non-secure versions, when there must be separate registers in the Secure (MPAMF_MBW_IDR_s) and Non-secure (MPAMF_MBW_IDR_ns) MPAM feature pages.
MPAMF_MBW_IDR can be accessed through the memory-mapped interfaces:
| Component | Frame | Offset | Instance |
|---|---|---|---|
| MPAM | MPAMF_BASE_s | 0x0040 | MPAMF_MBW_IDR_s |
Accesses on this interface are RO.
| Component | Frame | Offset | Instance |
|---|---|---|---|
| MPAM | MPAMF_BASE_ns | 0x0040 | MPAMF_MBW_IDR_ns |
Accesses on this interface are RO.