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PMCIDR0, Performance Monitors Component Identification Register 0

The PMCIDR0 characteristics are:

Purpose

Provides information to identify a Performance Monitor component.

For more information see 'About the Component identification scheme' in the Arm® Architecture Reference Manual, Armv8, for Armv8-A architecture profile, section H8 (About the External Debug Registers).

Configuration

Implementation of this register is OPTIONAL.

If ARMv8.3-DoPD is implemented, this register is in the Core power domain. If ARMv8.3-DoPD is not implemented, this register is in the Debug power domain.

This register is required for CoreSight compliance.

Attributes

PMCIDR0 is a 32-bit register.

Field descriptions

The PMCIDR0 bit assignments are:

313029282726252423222120191817161514131211109876543210
RES0PRMBL_0

Bits [31:8]

Reserved, RES0.

PRMBL_0, bits [7:0]

Preamble. Must read as 0x0D.

Accessing the PMCIDR0

PMCIDR0 can be accessed through the external debug interface:

ComponentOffsetInstance
PMU0xFF0PMCIDR0

This interface is accessible as follows:

  • When ARMv8.3-DoPD is not implemented or IsCorePowered() accesses to this register are RO.
  • Otherwise accesses to this register generate an error response.