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CP15ISB, Instruction Synchronization Barrier System instruction
The CP15ISB characteristics are:
Purpose
Performs an Instruction Synchronization Barrier.
Arm deprecates any use of this System instruction, and strongly recommends that software use the ISB instruction instead.
Configuration
This instruction is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to CP15ISB are UNKNOWN.
Attributes
CP15ISB is a 32-bit System instruction.
Field descriptions
This instruction has no applicable fields.
The value in the register specified by <Rt> is ignored.
Executing the CP15ISB instruction
Accesses to this instruction use the following encodings:
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0111 | 0b0101 | 0b100 |
if PSTATE.EL == EL0 then
if !ELUsingAArch32(EL1) && !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && SCTLR_EL1.CP15BEN == '0' then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> == '11' && SCTLR_EL2.CP15BEN == '0' then
UNDEFINED;
elsif ELUsingAArch32(EL1) && SCTLR.CP15BEN == '0' then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<E2H,TGE> != '11' && HSTR_EL2.T7 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then
AArch32.TakeHypTrapException(0x03);
else
CP15ISB();
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T7 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T7 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif ELUsingAArch32(EL1) && SCTLR.CP15BEN == '0' then
UNDEFINED;
else
CP15ISB();
elsif PSTATE.EL == EL2 then
if HSCTLR.CP15BEN == '0' then
UNDEFINED;
else
CP15ISB();
elsif PSTATE.EL == EL3 then
if SCTLR.CP15BEN == '0' then
UNDEFINED;
else
CP15ISB();