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RVBAR, Reset Vector Base Address Register
The RVBAR characteristics are:
Purpose
If EL3 is not implemented, contains the IMPLEMENTATION DEFINED address that execution starts from after reset when executing in AArch32 state.
Configuration
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to RVBAR are UNKNOWN.
This register is only implemented if the highest Exception level implemented is capable of using AArch32, and is not EL3.
Attributes
RVBAR is a 32-bit register.
Field descriptions
The RVBAR bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reset Address[31:1] | RES1 | ||||||||||||||||||||||||||||||
Bits [31:1]
Reset Address[31:1]. Bits [31:1] of the IMPLEMENTATION DEFINED address that execution starts from after reset when executing in 32-bit state.
Bit [0]
Reserved, RES1.
Accessing the RVBAR
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1100 | 0b0000 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if IsHighestEL(EL1) then
return RVBAR;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif !ELUsingAArch32(EL2) && SCR_EL3.<NS,EEL2> == '01' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
if IsHighestEL(EL2) then
return RVBAR;
else
UNDEFINED;
elsif PSTATE.EL == EL3 then
return MVBAR;