MDSCR_EL1, Monitor Debug System Control Register
The MDSCR_EL1 characteristics are:
Purpose
Main control register for the debug implementation.
Configuration
AArch64 System register MDSCR_EL1 bits [31:0] are architecturally mapped to AArch32 System register DBGDSCRext[31:0] .
Attributes
MDSCR_EL1 is a 64-bit register.
Field descriptions
The MDSCR_EL1 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | |||||||||||||||||||||||||||||||
| TFO | RXfull | TXfull | RES0 | RXO | TXU | RES0 | INTdis | TDA | RES0 | SC2 | RAZ/WI | MDE | HDE | KDE | TDCC | RES0 | ERR | RES0 | SS | ||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:32]
Reserved, RES0.
TFO, bit [31]
When ARMv8.4-Trace is implemented:
When ARMv8.4-Trace is implemented:
Trace Filter override. Used for save/restore of EDSCR.TFO.
When OSLSR_EL1.OSLK == 0, software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this bit holds the value of EDSCR.TFO. Reads and writes of this bit are indirect accesses to EDSCR.TFO.
Accessing this field has the following behavior:
- When OSLSR_EL1.OSLK == 1, access to this field is RW.
- When OSLSR_EL1.OSLK == 0, access to this field is RO.
Otherwise:
Otherwise:
Reserved, RES0.
RXfull, bit [30]
Used for save/restore of EDSCR.RXfull.
When OSLSR_EL1.OSLK == 0, software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this bit holds the value of EDSCR.RXfull. Reads and writes of this bit are indirect accesses to EDSCR.RXfull.
The architected behavior of this field determines the value it returns after a reset.
Accessing this field has the following behavior:
- When OSLSR_EL1.OSLK == 1, access to this field is RW.
- When OSLSR_EL1.OSLK == 0, access to this field is RO.
TXfull, bit [29]
Used for save/restore of EDSCR.TXfull.
When OSLSR_EL1.OSLK == 0, software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this bit holds the value of EDSCR.TXfull. Reads and writes of this bit are indirect accesses to EDSCR.TXfull.
The architected behavior of this field determines the value it returns after a reset.
Accessing this field has the following behavior:
- When OSLSR_EL1.OSLK == 1, access to this field is RW.
- When OSLSR_EL1.OSLK == 0, access to this field is RO.
Bit [28]
Reserved, RES0.
RXO, bit [27]
Used for save/restore of EDSCR.RXO.
When OSLSR_EL1.OSLK == 0, software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this bit holds the value of EDSCR.RXO. Reads and writes of this bit are indirect accesses to EDSCR.RXO.
The architected behavior of this field determines the value it returns after a reset.
Accessing this field has the following behavior:
- When OSLSR_EL1.OSLK == 1, access to this field is RW.
- When OSLSR_EL1.OSLK == 0, access to this field is RO.
TXU, bit [26]
Used for save/restore of EDSCR.TXU.
When OSLSR_EL1.OSLK == 0, software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this bit holds the value of EDSCR.TXU. Reads and writes of this bit are indirect accesses to EDSCR.TXU.
The architected behavior of this field determines the value it returns after a reset.
Accessing this field has the following behavior:
- When OSLSR_EL1.OSLK == 1, access to this field is RW.
- When OSLSR_EL1.OSLK == 0, access to this field is RO.
Bits [25:24]
Reserved, RES0.
INTdis, bits [23:22]
Used for save/restore of EDSCR.INTdis.
When OSLSR_EL1.OSLK == 0, and software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this field holds the value of EDSCR.INTdis. Reads and writes of this field are indirect accesses to EDSCR.INTdis.
The architected behavior of this field determines the value it returns after a reset.
Accessing this field has the following behavior:
- When OSLSR_EL1.OSLK == 1, access to this field is RW.
- When OSLSR_EL1.OSLK == 0, access to this field is RO.
TDA, bit [21]
Used for save/restore of EDSCR.TDA.
When OSLSR_EL1.OSLK == 0, software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this bit holds the value of EDSCR.TDA. Reads and writes of this bit are indirect accesses to EDSCR.TDA.
The architected behavior of this field determines the value it returns after a reset.
Accessing this field has the following behavior:
- When OSLSR_EL1.OSLK == 1, access to this field is RW.
- When OSLSR_EL1.OSLK == 0, access to this field is RO.
Bit [20]
Reserved, RES0.
SC2, bit [19]
When ARMv8.0-PCSample is implemented, ARMv8.1-VHE is implemented and ARMv8.2-PCSample is not implemented:
When ARMv8.0-PCSample is implemented, ARMv8.1-VHE is implemented and ARMv8.2-PCSample is not implemented:
Used for save/restore of EDSCR.SC2.
When OSLSR_EL1.OSLK == 0, software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this bit holds the value of EDSCR.SC2. Reads and writes of this bit are indirect accesses to EDSCR.SC2.
Accessing this field has the following behavior:
- When OSLSR_EL1.OSLK == 1, access to this field is RW.
- When OSLSR_EL1.OSLK == 0, access to this field is RO.
Otherwise:
Otherwise:
Reserved, RES0.
Bits [18:16]
Reserved, RAZ/WI.
Hardware must implement this field as RAZ/WI. Software must not rely on the register reading as zero, and must use a read-modify-write sequence to write to the register.
MDE, bit [15]
Monitor debug events. Enable Breakpoint, Watchpoint, and Vector Catch exceptions.
| MDE | Meaning |
|---|---|
| 0b0 |
Breakpoint, Watchpoint, and Vector Catch exceptions disabled. |
| 0b1 |
Breakpoint, Watchpoint, and Vector Catch exceptions enabled. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
HDE, bit [14]
Used for save/restore of EDSCR.HDE.
When OSLSR_EL1.OSLK == 0, software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this bit holds the value of EDSCR.HDE. Reads and writes of this bit are indirect accesses to EDSCR.HDE.
The architected behavior of this field determines the value it returns after a reset.
Accessing this field has the following behavior:
- When OSLSR_EL1.OSLK == 1, access to this field is RW.
- When OSLSR_EL1.OSLK == 0, access to this field is RO.
KDE, bit [13]
Local (kernel) debug enable. If ELD is using AArch64, enable debug exceptions within ELD. Permitted values are:
| KDE | Meaning |
|---|---|
| 0b0 |
Debug exceptions, other than Breakpoint Instruction exceptions, disabled within ELD. |
| 0b1 |
All debug exceptions enabled within ELD. |
RES0 if ELD is using AArch32.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
TDCC, bit [12]
Traps EL0 accesses to the Debug Communication Channel (DCC) registers to EL1, or to EL2 when it is implemented and enabled for the current Security state and HCR_EL2.TGE is 1, from both Execution states, as follows:
- In AArch64 state, MRS or MSR accesses to the following DCC registers are trapped, reported using EC syndrome value 0x18:
- MDCCSR_EL0.
- If not in Debug state, DBGDTR_EL0, DBGDTRTX_EL0, and DBGDTRRX_EL0.
- In AArch32 state, MRC or MCR accesses to the following registers are trapped, reported using EC syndrome value 0x05.
- DBGDSCRint, DBGDIDR, DBGDSAR, DBGDRAR.
- If not in Debug state, DBGDTRRXint, and DBGDTRTXint.
- In AArch32 state, LDC access to DBGDTRRXint and STC access to DBGDTRTXint are trapped, reported using EC syndrome value 0x06.
- In AArch32 state, MRRC accesses to DBGDSAR and DBGDRAR are trapped, reported using EC syndrome value 0x0C.
| TDCC | Meaning |
|---|---|
| 0b0 |
This control does not cause any instructions to be trapped. |
| 0b1 |
EL0 using AArch64: EL0 accesses to the AArch64 DCC registers are trapped. EL0 using AArch32: EL0 accesses to the AArch32 DCC registers are trapped. |
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bits [11:7]
Reserved, RES0.
ERR, bit [6]
Used for save/restore of EDSCR.ERR.
When OSLSR_EL1.OSLK == 0, software must treat this bit as UNK/SBZP.
When OSLSR_EL1.OSLK == 1, this bit holds the value of EDSCR.ERR. Reads and writes of this bit are indirect accesses to EDSCR.ERR.
The architected behavior of this field determines the value it returns after a reset.
Accessing this field has the following behavior:
- When OSLSR_EL1.OSLK == 1, access to this field is RW.
- When OSLSR_EL1.OSLK == 0, access to this field is RO.
Bits [5:1]
Reserved, RES0.
SS, bit [0]
Software step control bit. If ELD is using AArch64, enable Software step. Permitted values are:
| SS | Meaning |
|---|---|
| 0b0 |
Software step disabled |
| 0b1 |
Software step enabled. |
RES0 if ELD is using AArch32.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Accessing the MDSCR_EL1
Individual fields within this register might have restricted accessibility when OSLSR_EL1.OSLK == 0 (the OS lock is unlocked). See the field descriptions for more detail.
Accesses to this register use the following encodings:
MRS <Xt>, MDSCR_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b10 | 0b000 | 0b0000 | 0b0010 | 0b010 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.MDSCR_EL1 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '1x1' then
return NVMem[0x158];
else
return MDSCR_EL1;
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
UNDEFINED;
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return MDSCR_EL1;
elsif PSTATE.EL == EL3 then
return MDSCR_EL1;
MSR MDSCR_EL1, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b10 | 0b000 | 0b0000 | 0b0010 | 0b010 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.MDSCR_EL1 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDA> != '00' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.<NV2,NV1,NV> == '1x1' then
NVMem[0x158] = X[t];
else
MDSCR_EL1 = X[t];
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
UNDEFINED;
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TDA == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
MDSCR_EL1 = X[t];
elsif PSTATE.EL == EL3 then
MDSCR_EL1 = X[t];