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ERRFHICR0, Fault Handling Interrupt Configuration Register 0

The ERRFHICR0 characteristics are:

Purpose

Fault Handling Interrupt configuration register.

Configuration

This register is present only when the Fault Handling Interrupt is implemented and interrupt configuration registers use the recommended format. Otherwise, direct accesses to ERRFHICR0 are IMPLEMENTATION DEFINED.

ERRFHICR0 is implemented only as part of a memory-mapped group of error records.

Attributes

ERRFHICR0 is a 64-bit register.

Field descriptions

The ERRFHICR0 bit assignments are:

6362616059585756555453525150494847464544434241403938373635343332
RES0ADDR
ADDRRES0
313029282726252423222120191817161514131211109876543210

Bits [63:56]

Reserved, RES0.

ADDR, bits [55:2]

Message Signaled Interrupt address. Specifies the address that the component writes to when signaling an interrupt.

The size of a physical address is IMPLEMENTATION DEFINED. Unimplemented high-order physical address bits are RES0.

The following resets apply:

  • On an Error recovery reset, this field resets to an architecturally UNKNOWN value.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

Bits [1:0]

Reserved, RES0.

Accessing the ERRFHICR0

ERRFHICR0 can be accessed through the memory-mapped interfaces:

ComponentOffset
RAS0xE80

Accesses on this interface are RW.