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ERRFHICR1, Fault Handling Interrupt Configuration Register 1

The ERRFHICR1 characteristics are:

Purpose

Fault Handling Interrupt configuration register.

Configuration

This register is present only when the Fault Handling Interrupt is implemented and interrupt configuration registers use the recommended format. Otherwise, direct accesses to ERRFHICR1 are IMPLEMENTATION DEFINED.

ERRFHICR1 is implemented only as part of a memory-mapped group of error records.

Attributes

ERRFHICR1 is a 32-bit register.

Field descriptions

The ERRFHICR1 bit assignments are:

313029282726252423222120191817161514131211109876543210
DATA

DATA, bits [31:0]

Payload for a message signaled interrupt.

The following resets apply:

  • On an Error recovery reset, this field resets to an architecturally UNKNOWN value.

  • On a Cold reset, this field resets to an architecturally UNKNOWN value.

Accessing the ERRFHICR1

ERRFHICR1 can be accessed through the memory-mapped interfaces:

ComponentOffset
RAS0xE88

Accesses on this interface are RW.