ERRPIDR1, Peripheral Identification Register 1
The ERRPIDR1 characteristics are:
Provides discovery information about the component.
For more information, see 'About the Peripheral identification scheme'.
Implementation of this register is OPTIONAL.
ERRPIDR1 is implemented only as part of a memory-mapped group of error records.
ERRPIDR1 is a 32-bit register.
The ERRPIDR1 bit assignments are:
DES_0, bits [7:4]
Designer, JEP106 identification code, bits [3:0]. ERRPIDR1.DES_0 and ERRPIDR2.DES_1 together form the JEDEC-assigned JEP106 identification code for the designer of the component. The parity bit in the JEP106 identification code is not included. The code identifies the designer of the component, which might not be not the same as the implementer of the device containing the component. To obtain a number, or to see the assignment of these codes, contact JEDEC http://www.jedec.org.
For a component designed by Arm Limited, the JEP106 identification code is 0x3B.
PART_1, bits [3:0]
Part number, bits [11:8].
The part number is selected by the designer of the component. The designer chooses whether to use a 12-bit or a 16-bit part number:
- If a 12-bit part number is used, it is stored in ERRPIDR1.PART_1 and ERRPIDR0.PART_0. There are 8 bits, ERRPIDR2.REVISION and ERRPIDR3.REVAND, available to define the revision of the component.
- If a 16-bit part number is used, it is stored in ERRPIDR2.PART_2, ERRPIDR1.PART_1 and ERRPIDR0.PART_0. There are 4 bits, ERRPIDR3.REVISION, available to define the revision of the component.
Accessing the ERRPIDR1
ERRPIDR1 can be accessed through the memory-mapped interfaces:
Accesses on this interface are RO.