GICR_IGRPMODR<n>E, Interrupt Group Modifier Registers, n = 1 - 2
The GICR_IGRPMODR<n>E characteristics are:
When GICD_CTLR.DS==0, this register together with the GICR_IGROUPR<n>E registers, controls whether the corresponding interrupt is in:
- Secure Group 0.
- Non-secure Group 1.
- When System register access is enabled, Secure Group 1.
This register is present only when GICv3.1 is implemented. Otherwise, direct accesses to GICR_IGRPMODR<n>E are RES0.
When GICD_CTLR.DS==0, this register is Secure.
A copy of this register is provided for each Redistributor.
GICR_IGRPMODR<n>E is a 32-bit register.
The GICR_IGRPMODR<n>E bit assignments are:
|Group_modifier_bit<x>, bit [x], for x = 0 to 31|
Group_modifier_bit<x>, bit [x], for x = 0 to 31
Group modifier bit. In implementations where affinity routing is enabled for the Security state of an interrupt, the bit that corresponds to the interrupt is concatenated with the equivalent bit in GICR_IGROUPR<n>E to form a 2-bit field that defines an interrupt group:
|Group modifier bit||Group status bit||Definition||Short name|
|0b0||0b0||Secure Group 0||G0S|
|0b0||0b1||Non-secure Group 1||G1NS|
|0b1||0b0||Secure Group 1||G1S|
|0b1||0b1||Reserved, treated as Non-secure Group 1||-|
This field resets to an architecturally UNKNOWN value.
For INTID m, when DIV and MOD are the integer division and modulo operations:
- The corresponding GICR_IGRPMODR<n>E number, n, is given by n = (m-1024) DIV 32.
- The offset of the required GICR_IGRPMODR<n>E is (0xD00 + (4*n)).
- The bit number of the required group modifier bit in this register is (m-1024) MOD 32.
Accessing the GICR_IGRPMODR<n>E
When affinity routing is not enabled for the Security state of an interrupt in GICR_IGRPMODR<n>E, the corresponding bit is RES0.
When GICD_CTLR.DS==0, the register is RAZ/WI to Non-secure accesses.
Bits corresponding to unimplemented interrupts are RAZ/WI.
GICR_IGRPMODR<n>E can be accessed through the memory-mapped interfaces:
|GIC Redistributor||SGI_base||0x0D00 + 4n||GICR_IGRPMODR<n>E|
This interface is accessible as follows:
- When GICD_CTLR.DS == 0b0 accesses to this register are RW.
- When IsAccessSecure() accesses to this register are RW.
- When !IsAccessSecure() accesses to this register are RW.