DBGDRAR, Debug ROM Address Register
The DBGDRAR characteristics are:
Purpose
Defines the base physical address of a 4KB-aligned memory-mapped debug component, usually a ROM table that locates and describes the memory-mapped debug components in the system. Armv8 deprecates any use of this register.
Configuration
AArch32 System register DBGDRAR bits [63:0] are architecturally mapped to AArch64 System register MDRAR_EL1[63:0] .
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to DBGDRAR are UNDEFINED.
If EL1 cannot use AArch32 then the implementation of this register is OPTIONAL and deprecated.
Attributes
DBGDRAR is a 64-bit register that can also be accessed as a 32-bit value. If it is accessed as a 32-bit register, bits [31:0] are read.
Field descriptions
The DBGDRAR bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | ROMADDR[47:12] | ||||||||||||||||||||||||||||||
| ROMADDR[47:12] | RES0 | Valid | |||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:48]
Reserved, RES0.
ROMADDR[47:12], bits [47:12]
Bits[47:12] of the ROM table physical address.
If the physical address size in bits (PAsize) is less than 48 then the register bits corresponding to ROMADDR [47:PAsize] are RES0.
Bits [11:0] of the ROM table physical address are zero.
Arm strongly recommends that bits ROMADDR[(PAsize-1):32] are zero in any system that supports AArch32 at the highest implemented Exception level.
In an implementation that includes EL3, ROMADDR is an address in Non-secure memory. It is IMPLEMENTATION DEFINED whether the ROM table is also accessible in Secure memory.
If DBGDRAR.Valid == 0b00, then this field is UNKNOWN.
Bits [11:2]
Reserved, RES0.
Valid, bits [1:0]
This field indicates whether the ROM Table address is valid.
| Valid | Meaning |
|---|---|
| 0b00 |
ROM Table address is not valid. Software must ignore ROMADDR. |
| 0b11 |
ROM Table address is valid. |
Other values are reserved.
Accessing the DBGDRAR
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1110 | 0b000 | 0b0001 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then
if !ELUsingAArch32(EL1) && MDSCR_EL1.TDCC == '1' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x05);
else
AArch64.AArch32SystemAccessTrap(EL1, 0x05);
elsif ELUsingAArch32(EL1) && DBGDSCRext.UDCCdis == '1' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x05);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then
AArch32.TakeHypTrapException(0x00);
else
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && (HCR_EL2.TGE == '1' || MDCR_EL2.<TDE,TDRA> != '00') then
AArch64.AArch32SystemAccessTrap(EL2, 0x05);
elsif EL2Enabled() && ELUsingAArch32(EL2) && (HCR.TGE == '1' || HDCR.<TDE,TDRA> != '00') then
AArch32.TakeHypTrapException(0x05);
else
return DBGDRAR<31:0>;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDRA> != '00' then
AArch64.AArch32SystemAccessTrap(EL2, 0x05);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDRA> != '00' then
AArch32.TakeHypTrapException(0x05);
else
return DBGDRAR<31:0>;
elsif PSTATE.EL == EL2 then
return DBGDRAR<31:0>;
elsif PSTATE.EL == EL3 then
return DBGDRAR<31:0>;
MRRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm>
| coproc | CRm | opc1 |
|---|---|---|
| 0b1110 | 0b0001 | 0b0000 |
if PSTATE.EL == EL0 then
if !ELUsingAArch32(EL1) && MDSCR_EL1.TDCC == '1' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x0C);
else
AArch64.AArch32SystemAccessTrap(EL1, 0x0C);
elsif ELUsingAArch32(EL1) && DBGDSCRext.UDCCdis == '1' then
if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x0C);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then
AArch32.TakeHypTrapException(0x00);
else
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && (HCR_EL2.TGE == '1' || MDCR_EL2.<TDE,TDRA> != '00') then
AArch64.AArch32SystemAccessTrap(EL2, 0x0C);
elsif EL2Enabled() && ELUsingAArch32(EL2) && (HCR.TGE == '1' || HDCR.<TDE,TDRA> != '00') then
AArch32.TakeHypTrapException(0x0C);
else
return DBGDRAR;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.<TDE,TDRA> != '00' then
AArch64.AArch32SystemAccessTrap(EL2, 0x0C);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.<TDE,TDRA> != '00' then
AArch32.TakeHypTrapException(0x0C);
else
return DBGDRAR;
elsif PSTATE.EL == EL2 then
return DBGDRAR;
elsif PSTATE.EL == EL3 then
return DBGDRAR;