ICC_SRE, Interrupt Controller System Register Enable register
The ICC_SRE characteristics are:
Purpose
Controls whether the System register interface or the memory-mapped interface to the GIC CPU interface is used for EL0 and EL1.
Configuration
AArch32 System register ICC_SRE bits [31:0] (S) are architecturally mapped to AArch64 System register ICC_SRE_EL1[31:0] (S) .
AArch32 System register ICC_SRE bits [31:0] (NS) are architecturally mapped to AArch64 System register ICC_SRE_EL1[31:0] (NS) .
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to ICC_SRE are UNDEFINED.
Attributes
ICC_SRE is a 32-bit register.
Field descriptions
The ICC_SRE bit assignments are:
Bits [31:3]
Reserved, RES0.
DIB, bit [2]
Disable IRQ bypass.
| DIB | Meaning |
|---|---|
| 0b0 |
IRQ bypass enabled. |
| 0b1 |
IRQ bypass disabled. |
If EL3 is implemented and GICD_CTLR.DS == 0, this field is a read-only alias of ICC_MSRE.DIB.
If EL3 is implemented and GICD_CTLR.DS == 1, and EL2 is not implemented, this field is a read-write alias of ICC_MSRE.DIB.
If EL3 is not implemented and EL2 is implemented, this field is a read-only alias of ICC_HSRE.DIB.
If GICD_CTLR.DS == 1 and EL2 is implemented, this field is a read-only alias of ICC_HSRE.DIB.
In systems that do not support IRQ bypass, this field is RAO/WI.
This field resets to 0.
DFB, bit [1]
Disable FIQ bypass.
| DFB | Meaning |
|---|---|
| 0b0 |
FIQ bypass enabled. |
| 0b1 |
FIQ bypass disabled. |
If EL3 is implemented and GICD_CTLR.DS == 0, this field is a read-only alias of ICC_MSRE.DFB.
If EL3 is implemented and GICD_CTLR.DS == 1, and EL2 is not implemented, this field is a read-write alias of ICC_MSRE.DFB.
If EL3 is not implemented and EL2 is implemented, this field is a read-only alias of ICC_HSRE.DFB.
If GICD_CTLR.DS == 1 and EL2 is implemented, this field is a read-only alias of ICC_HSRE.DFB.
In systems that do not support FIQ bypass, this field is RAO/WI.
This field resets to 0.
SRE, bit [0]
System Register Enable.
| SRE | Meaning |
|---|---|
| 0b0 |
The memory-mapped interface must be used. Accesses at EL1 to any ICC_* System register other than ICC_SRE are UNDEFINED. |
| 0b1 |
The System register interface for the current Security state is enabled. |
If software changes this bit from 1 to 0 in the Secure instance of this register, the results are UNPREDICTABLE.
If an implementation supports only a System register interface to the GIC CPU interface, this bit is RAO/WI.
If EL3 is implemented and using AArch64:
- When ICC_SRE_EL3.SRE==0 the Secure copy of this bit is RAZ/WI.
- When ICC_SRE_EL3.SRE==0 the Non-secure copy of this bit is RAZ/WI.
If EL3 is implemented and using AArch32:
- When ICC_MSRE.SRE==0 the Secure copy of this bit is RAZ/WI.
- When ICC_MSRE.SRE==0 the Non-secure copy of this bit is RAZ/WI.
If EL2 is implemented and using AArch64:
- When ICC_SRE_EL2.SRE==0 the Non-secure copy of this bit is RAZ/WI.
If EL2 is implemented and using AArch32:
- When ICC_HSRE.SRE==0 the Non-secure copy of this bit is RAZ/WI.
This field resets to 0.
Accessing the ICC_SRE
The GIC architecture permits, but does not require, that registers can be shared between memory-mapped registers and the equivalent System registers. This means that if the memory-mapped registers have been accessed while ICC_SRE.SRE==0, then the System registers might be modified. Therefore, software must only rely on the reset values of the System registers if there has been no use of the GIC functionality while the memory-mapped registers are in use. Otherwise, the System register values must be treated as UNKNOWN.
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1100 | 0b1100 | 0b101 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then
AArch32.TakeHypTrapException(0x03);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && ICC_SRE_EL3.Enable == '0' then
UNDEFINED;
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && ICC_SRE_EL3.Enable == '0' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif ICC_MSRE.Enable == '0' then
UNDEFINED;
elsif HaveEL(EL3) then
if SCR_EL3.NS == '0' then
return ICC_SRE_S;
else
return ICC_SRE_NS;
else
return ICC_SRE;
elsif PSTATE.EL == EL3 then
if SCR_EL3.NS == '0' then
return ICC_SRE_S;
else
return ICC_SRE_NS;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1100 | 0b1100 | 0b101 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then
AArch32.TakeHypTrapException(0x03);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && ICC_SRE_EL3.Enable == '0' then
UNDEFINED;
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && ICC_SRE_EL3.Enable == '0' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif ICC_MSRE.Enable == '0' then
UNDEFINED;
elsif HaveEL(EL3) then
if SCR_EL3.NS == '0' then
ICC_SRE_S = R[t];
else
ICC_SRE_NS = R[t];
else
ICC_SRE = R[t];
elsif PSTATE.EL == EL3 then
if SCR_EL3.NS == '0' then
ICC_SRE_S = R[t];
else
ICC_SRE_NS = R[t];