ICH_EISR, Interrupt Controller End of Interrupt Status Register
The ICH_EISR characteristics are:
Purpose
Indicates which List registers have outstanding EOI maintenance interrupts.
Configuration
AArch32 System register ICH_EISR bits [31:0] are architecturally mapped to AArch64 System register ICH_EISR_EL2[31:0] .
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to ICH_EISR are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
Attributes
ICH_EISR is a 32-bit register.
Field descriptions
The ICH_EISR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | Status<n>, bit [n], for n = 0 to 15 |
Bits [31:16]
Reserved, RES0.
Status<n>, bit [n], for n = 0 to 15
EOI maintenance interrupt status bit for List register <n>:
Status<n> | Meaning |
---|---|
0b0 |
List register <n>, ICH_LR<n>, does not have an EOI maintenance interrupt. |
0b1 |
List register <n>, ICH_LR<n>, has an EOI maintenance interrupt that has not been handled. |
For any ICH_LR<n>, the corresponding status bit is set to 1 if all of the following are true:
- ICH_LRC<n>.State is 0b00.
- ICH_LRC<n>.HW is 0.
- ICH_LRC<n>.EOI (bit [9]) is 1, indicating that when the interrupt corresponding to that List register is deactivated, a maintenance interrupt is asserted.
This field resets to 0.
Accessing the ICH_EISR
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b100 | 0b1100 | 0b1011 | 0b011 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then if ICC_HSRE.SRE == '0' then UNDEFINED; else return ICH_EISR; elsif PSTATE.EL == EL3 then if ICC_MSRE.SRE == '0' then UNDEFINED; else return ICH_EISR;