ICH_HCR, Interrupt Controller Hyp Control Register
The ICH_HCR characteristics are:
Purpose
Controls the environment for VMs.
Configuration
AArch32 System register ICH_HCR bits [31:0] are architecturally mapped to AArch64 System register ICH_HCR_EL2[31:0] .
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to ICH_HCR are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
Attributes
ICH_HCR is a 32-bit register.
Field descriptions
The ICH_HCR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EOIcount | RES0 | TDIR | TSEI | TALL1 | TALL0 | TC | RES0 | vSGIEOICount | VGrp1DIE | VGrp1EIE | VGrp0DIE | VGrp0EIE | NPIE | LRENPIE | UIE | En |
EOIcount, bits [31:27]
This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation. That is either:
- A virtual write to EOIR with a valid interrupt identifier that is not in the LPI range (that is < 8192) when EOI mode is zero and no List Register was found.
- A virtual write to DIR with a valid interrupt identifier that is not in the LPI range (that is < 8192) when EOI mode is one and no List Register was found.
This allows software to manage more active interrupts than there are implemented List Registers.
It is CONSTRAINED UNPREDICTABLE whether a virtual write to EOIR that does not clear a bit in the Active Priorities registers (ICH_AP0R<n>/ICH_AP1R<n>) increments EOIcount. Permitted behaviors are:
- Increment EOIcount.
- Leave EOIcount unchanged.
This field resets to 0.
Bits [26:15]
Reserved, RES0.
TDIR, bit [14]
Trap Non-secure EL1 writes to ICC_DIR and ICV_DIR.
TDIR | Meaning |
---|---|
0b0 |
Non-secure EL1 writes of ICC_DIR and ICV_DIR are not trapped to EL2, unless trapped by other mechanisms. |
0b1 |
Non-secure EL1 writes of ICV_DIR are trapped to EL2. It is IMPLEMENTATION DEFINED whether Non-secure writes of ICC_DIR are trapped. Not trapping ICC_DIR writes is DEPRECATED. |
Support for this bit is OPTIONAL, with support indicated by ICH_VTR.
If the implementation does not support this trap, this bit is RES0.
Arm deprecates not including this trap bit.
This field resets to 0.
TSEI, bit [13]
Trap all locally generated SEIs. This bit allows the hypervisor to intercept locally generated SEIs that would otherwise be taken at Non-secure EL1.
TSEI | Meaning |
---|---|
0b0 |
Locally generated SEIs do not cause a trap to EL2. |
0b1 |
Locally generated SEIs trap to EL2. |
If ICH_VTR.SEIS is 0, this bit is RES0.
This field resets to 0.
TALL1, bit [12]
Trap all Non-secure EL1 accesses to ICC_* and ICV_* System registers for Group 1 interrupts to EL2.
TALL1 | Meaning |
---|---|
0b0 |
Non-secure EL1 accesses to ICC_* and ICV_* registers for Group 1 interrupts proceed as normal. |
0b1 |
Non-secure EL1 accesses to ICC_* and ICV_* registers for Group 1 interrupts trap to EL2. |
This field resets to 0.
TALL0, bit [11]
Trap all Non-secure EL1 accesses to ICC_* and ICV_* System registers for Group 0 interrupts to EL2.
TALL0 | Meaning |
---|---|
0b0 |
Non-secure EL1 accesses to ICC_* and ICV_* registers for Group 0 interrupts proceed as normal. |
0b1 |
Non-secure EL1 accesses to ICC_* and ICV_* registers for Group 0 interrupts trap to EL2. |
This field resets to 0.
TC, bit [10]
Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2.
TC | Meaning |
---|---|
0b0 |
Non-secure EL1 accesses to common registers proceed as normal. |
0b1 |
Non-secure EL1 accesses to common registers trap to EL2. |
This affects accesses to ICC_SGI0R, ICC_SGI1R, ICC_ASGI1R, ICC_CTLR, ICC_DIR, ICC_PMR, ICC_RPR, ICV_CTLR, ICV_DIR, ICV_PMR, and ICV_RPR.
This field resets to 0.
Bit [9]
Reserved, RES0.
vSGIEOICount, bit [8]
When FEAT_GICv4p1 is implemented:
When FEAT_GICv4p1 is implemented:
Controls whether deactivation of virtual SGIs can increment ICH_HCR_EL2.EOIcount
vSGIEOICount | Meaning |
---|---|
0b0 |
Deactivation of virtual SGIs can increment ICH_HCR.EOIcount. |
0b1 |
Deactivation of virtual SGIs does not increment ICH_HCR.EOIcount. |
This field resets to 0.
Otherwise:
Otherwise:
Reserved, RES0.
VGrp1DIE, bit [7]
VM Group 1 Disabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 1 interrupts from the virtual CPU interface to the connected vPE is disabled:
VGrp1DIE | Meaning |
---|---|
0b0 |
Maintenance interrupt disabled. |
0b1 |
Maintenance interrupt signaled when ICH_VMCR.VENG1 is 0. |
This field resets to 0.
VGrp1EIE, bit [6]
VM Group 1 Enabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 1 interrupts from the virtual CPU interface to the connected vPE is enabled:
VGrp1EIE | Meaning |
---|---|
0b0 |
Maintenance interrupt disabled. |
0b1 |
Maintenance interrupt signaled when ICH_VMCR.VENG1 is 1. |
This field resets to 0.
VGrp0DIE, bit [5]
VM Group 0 Disabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 0 interrupts from the virtual CPU interface to the connected vPE is disabled:
VGrp0DIE | Meaning |
---|---|
0b0 |
Maintenance interrupt disabled. |
0b1 |
Maintenance interrupt signaled when ICH_VMCR.VENG0 is 0. |
This field resets to 0.
VGrp0EIE, bit [4]
VM Group 0 Enabled Interrupt Enable. Enables the signaling of a maintenance interrupt while signaling of Group 0 interrupts from the virtual CPU interface to the connected vPE is enabled:
VGrp0EIE | Meaning |
---|---|
0b0 |
Maintenance interrupt disabled. |
0b1 |
Maintenance interrupt signaled when ICH_VMCR.VENG0 is 1. |
This field resets to 0.
NPIE, bit [3]
No Pending Interrupt Enable. Enables the signaling of a maintenance interrupt when there are no List registers with the State field set to 0b01 (pending):
NPIE | Meaning |
---|---|
0b0 |
Maintenance interrupt disabled. |
0b1 |
Maintenance interrupt signaled while the List registers contain no interrupts in the pending state. |
This field resets to 0.
LRENPIE, bit [2]
List Register Entry Not Present Interrupt Enable. Enables the signaling of a maintenance interrupt while the virtual CPU interface does not have a corresponding valid List register entry for an EOI request:
LRENPIE | Meaning |
---|---|
0b0 |
Maintenance interrupt disabled. |
0b1 |
Maintenance interrupt is asserted while the EOIcount field is not 0. |
This field resets to 0.
UIE, bit [1]
Underflow Interrupt Enable. Enables the signaling of a maintenance interrupt when the List registers are empty, or hold only one valid entry:
UIE | Meaning |
---|---|
0b0 |
Maintenance interrupt disabled. |
0b1 |
Maintenance interrupt is asserted if none, or only one, of the List register entries is marked as a valid interrupt. |
This field resets to 0.
En, bit [0]
Enable. Global enable bit for the virtual CPU interface:
En | Meaning |
---|---|
0b0 |
Virtual CPU interface operation disabled. |
0b1 |
Virtual CPU interface operation enabled. |
When this field is set to 0:
- The virtual CPU interface does not signal any maintenance interrupts.
- The virtual CPU interface does not signal any virtual interrupts.
- A read of ICV_IAR0, ICV_IAR1, GICV_IAR or GICV_AIAR returns a spurious interrupt ID.
This field resets to 0.
Accessing the ICH_HCR
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b100 | 0b1100 | 0b1011 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then if ICC_HSRE.SRE == '0' then UNDEFINED; else return ICH_HCR; elsif PSTATE.EL == EL3 then if ICC_MSRE.SRE == '0' then UNDEFINED; else return ICH_HCR;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b100 | 0b1100 | 0b1011 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then if ICC_HSRE.SRE == '0' then UNDEFINED; else ICH_HCR = R[t]; elsif PSTATE.EL == EL3 then if ICC_MSRE.SRE == '0' then UNDEFINED; else ICH_HCR = R[t];