ICH_MISR, Interrupt Controller Maintenance Interrupt State Register
The ICH_MISR characteristics are:
Purpose
Indicates which maintenance interrupts are asserted.
Configuration
AArch32 System register ICH_MISR bits [31:0] are architecturally mapped to AArch64 System register ICH_MISR_EL2[31:0] .
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to ICH_MISR are UNDEFINED.
If EL2 is not implemented, this register is RES0 from EL3.
Attributes
ICH_MISR is a 32-bit register.
Field descriptions
The ICH_MISR bit assignments are:
Bits [31:8]
Reserved, RES0.
VGrp1D, bit [7]
vPE Group 1 Disabled.
VGrp1D | Meaning |
---|---|
0b0 |
vPE Group 1 Disabled maintenance interrupt not asserted. |
0b1 |
vPE Group 1 Disabled maintenance interrupt asserted. |
This maintenance interrupt is asserted when ICH_HCR.VGrp1DIE is 1 and ICH_VMCR.VENG0 is 0.
This field resets to 0.
VGrp1E, bit [6]
vPE Group 1 Enabled.
VGrp1E | Meaning |
---|---|
0b0 |
vPE Group 1 Enabled maintenance interrupt not asserted. |
0b1 |
vPE Group 1 Enabled maintenance interrupt asserted. |
This maintenance interrupt is asserted when ICH_HCR.VGrp1EIE is 1 and ICH_VMCR.VENG1 is 1.
This field resets to 0.
VGrp0D, bit [5]
vPE Group 0 Disabled.
VGrp0D | Meaning |
---|---|
0b0 |
vPE Group 0 Disabled maintenance interrupt not asserted. |
0b1 |
vPE Group 0 Disabled maintenance interrupt asserted. |
This maintenance interrupt is asserted when ICH_HCR.VGrp0DIE is 1 and ICH_VMCR.VENG0 is 0.
This field resets to 0.
VGrp0E, bit [4]
vPE Group 0 Enabled.
VGrp0E | Meaning |
---|---|
0b0 |
vPE Group 0 Enabled maintenance interrupt not asserted. |
0b1 |
vPE Group 0 Enabled maintenance interrupt asserted. |
This maintenance interrupt is asserted when ICH_HCR.VGrp0EIE is 1 and ICH_VMCR.VENG0 is 1.
This field resets to 0.
NP, bit [3]
No Pending.
NP | Meaning |
---|---|
0b0 |
No Pending maintenance interrupt not asserted. |
0b1 |
No Pending maintenance interrupt asserted. |
This maintenance interrupt is asserted when ICH_HCR.NPIE is 1 and no List register is in pending state.
This field resets to 0.
LRENP, bit [2]
List Register Entry Not Present.
LRENP | Meaning |
---|---|
0b0 |
List Register Entry Not Present maintenance interrupt not asserted. |
0b1 |
List Register Entry Not Present maintenance interrupt asserted. |
This maintenance interrupt is asserted when ICH_HCR.LRENPIE is 1 and ICH_HCR.EOIcount is non-zero.
This field resets to 0.
U, bit [1]
Underflow.
U | Meaning |
---|---|
0b0 |
Underflow maintenance interrupt not asserted. |
0b1 |
Underflow maintenance interrupt asserted. |
This maintenance interrupt is asserted when ICH_HCR.UIE is 1 and zero or one of the List register entries are marked as a valid interrupt, that is, if the corresponding ICH_LRC<n>.State bits do not equal 0x0.
This field resets to 0.
EOI, bit [0]
End Of Interrupt.
EOI | Meaning |
---|---|
0b0 |
End Of Interrupt maintenance interrupt not asserted. |
0b1 |
End Of Interrupt maintenance interrupt asserted. |
This maintenance interrupt is asserted when at least one bit in ICH_EISR is 1.
This field resets to 0.
Accessing the ICH_MISR
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b100 | 0b1100 | 0b1011 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then if ICC_HSRE.SRE == '0' then UNDEFINED; else return ICH_MISR; elsif PSTATE.EL == EL3 then if ICC_MSRE.SRE == '0' then UNDEFINED; else return ICH_MISR;