ICV_RPR, Interrupt Controller Virtual Running Priority Register
The ICV_RPR characteristics are:
Purpose
Indicates the Running priority of the virtual CPU interface.
Configuration
AArch32 System register ICV_RPR performs the same function as AArch64 System register ICV_RPR_EL1.
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to ICV_RPR are UNDEFINED.
Attributes
ICV_RPR is a 32-bit register.
Field descriptions
The ICV_RPR bit assignments are:
Bits [31:8]
Reserved, RES0.
Priority, bits [7:0]
The current running priority on the virtual CPU interface. This is the group priority of the current active virtual interrupt.
The priority returned is the group priority as if the BPR for the current Exception level and Security state was set to the minimum value of BPR for the number of implemented priority bits.
If 8 bits of priority are implemented the group priority is bits[7:1] of the priority.
Accessing the ICV_RPR
If there are no active interrupts on the virtual CPU interface, or all active interrupts have undergone a priority drop, the value returned is the Idle priority.
Software cannot determine the number of implemented priority bits from a read of this register.
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1100 | 0b1011 | 0b011 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then
UNDEFINED;
elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.<IRQ,FIQ> == '11' then
UNDEFINED;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TC == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && ICH_HCR.TC == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.FMO == '1' then
return ICV_RPR;
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.IMO == '1' then
return ICV_RPR;
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.FMO == '1' then
return ICV_RPR;
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.IMO == '1' then
return ICV_RPR;
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.<IRQ,FIQ> == '11' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch32.TakeMonitorTrapException();
else
return ICC_RPR;
elsif PSTATE.EL == EL2 then
if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then
UNDEFINED;
elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && ELUsingAArch32(EL3) && SCR.<IRQ,FIQ> == '11' then
UNDEFINED;
elsif ICC_HSRE.SRE == '0' then
UNDEFINED;
elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.<IRQ,FIQ> == '11' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.<IRQ,FIQ> == '11' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch32.TakeMonitorTrapException();
else
return ICC_RPR;
elsif PSTATE.EL == EL3 then
if ICC_MSRE.SRE == '0' then
UNDEFINED;
else
return ICC_RPR;