ID_MMFR0, Memory Model Feature Register 0
The ID_MMFR0 characteristics are:
Purpose
Provides information about the implemented memory model and memory management support in AArch32 state.
Must be interpreted with ID_MMFR1, ID_MMFR2, ID_MMFR3, and ID_MMFR4.
For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.
Configuration
AArch32 System register ID_MMFR0 bits [31:0] are architecturally mapped to AArch64 System register ID_MMFR0_EL1[31:0] .
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to ID_MMFR0 are UNDEFINED.
Attributes
ID_MMFR0 is a 32-bit register.
Field descriptions
The ID_MMFR0 bit assignments are:
InnerShr, bits [31:28]
Innermost Shareability. Indicates the innermost shareability domain implemented. Defined values are:
| InnerShr | Meaning |
|---|---|
| 0b0000 |
Implemented as Non-cacheable. |
| 0b0001 |
Implemented with hardware coherency support. |
| 0b1111 |
Shareability ignored. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000, 0b0001, and 0b1111.
This field is valid only if the implementation supports two levels of shareability, as indicated by ID_MMFR0.ShareLvl having the value 0b0001.
When ID_MMFR0.ShareLvl is zero, this field is UNKNOWN.
FCSE, bits [27:24]
Indicates whether the implementation includes the FCSE. Defined values are:
| FCSE | Meaning |
|---|---|
| 0b0000 |
Not supported. |
| 0b0001 |
Support for FCSE. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0000.
AuxReg, bits [23:20]
Auxiliary Registers. Indicates support for Auxiliary registers. Defined values are:
| AuxReg | Meaning |
|---|---|
| 0b0000 |
None supported. |
| 0b0001 |
Support for Auxiliary Control Register only. |
| 0b0010 |
Support for Auxiliary Fault Status Registers (AIFSR and ADFSR) and Auxiliary Control Register. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0010.
Accesses to unimplemented Auxiliary registers are UNDEFINED.
TCM, bits [19:16]
Indicates support for TCMs and associated DMAs. Defined values are:
| TCM | Meaning |
|---|---|
| 0b0000 |
Not supported. |
| 0b0001 |
Support is IMPLEMENTATION DEFINED. Armv7 requires this setting. |
| 0b0010 |
Support for TCM only, Armv6 implementation. |
| 0b0011 |
Support for TCM and DMA, Armv6 implementation. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0000.
ShareLvl, bits [15:12]
Shareability Levels. Indicates the number of shareability levels implemented. Defined values are:
| ShareLvl | Meaning |
|---|---|
| 0b0000 |
One level of shareability implemented. |
| 0b0001 |
Two levels of shareability implemented. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0001.
OuterShr, bits [11:8]
Outermost Shareability. Indicates the outermost shareability domain implemented. Defined values are:
| OuterShr | Meaning |
|---|---|
| 0b0000 |
Implemented as Non-cacheable. |
| 0b0001 |
Implemented with hardware coherency support. |
| 0b1111 |
Shareability ignored. |
All other values are reserved.
In Armv8-A, the permitted values are 0b0000, 0b0001, and 0b1111.
PMSA, bits [7:4]
Indicates support for a PMSA. Defined values are:
| PMSA | Meaning |
|---|---|
| 0b0000 |
Not supported. |
| 0b0001 |
Support for IMPLEMENTATION DEFINED PMSA. |
| 0b0010 |
Support for PMSAv6, with a Cache Type Register implemented. |
| 0b0011 |
Support for PMSAv7, with support for memory subsections. Armv7-R profile. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0000.
VMSA, bits [3:0]
Indicates support for a VMSA. Defined values are:
| VMSA | Meaning |
|---|---|
| 0b0000 |
Not supported. |
| 0b0001 |
Support for IMPLEMENTATION DEFINED VMSA. |
| 0b0010 |
Support for VMSAv6, with Cache and TLB Type Registers implemented. |
| 0b0011 |
Support for VMSAv7, with support for remapping and the Access flag. ARMv7-A profile. |
| 0b0100 |
As for 0b0011, and adds support for the PXN bit in the Short-descriptor translation table format descriptors. |
| 0b0101 |
As for 0b0100, and adds support for the Long-descriptor translation table format. |
All other values are reserved.
In Armv8-A, the only permitted value is 0b0101.
Accessing the ID_MMFR0
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0000 | 0b0001 | 0b100 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID3 == '1' then
AArch32.TakeHypTrapException(0x03);
else
return ID_MMFR0;
elsif PSTATE.EL == EL2 then
return ID_MMFR0;
elsif PSTATE.EL == EL3 then
return ID_MMFR0;