MAIR1, Memory Attribute Indirection Register 1
The MAIR1 characteristics are:
Purpose
Along with MAIR0, provides the memory attribute encodings corresponding to the possible AttrIndx values in a Long-descriptor format translation table entry for stage 1 translations.
AttrIndx[2] indicates the MAIR register to be used:
- When AttrIndx[2] is 0, MAIR0 is used.
- When AttrIndx[2] is 1, MAIR1 is used.
Configuration
AArch32 System register MAIR1 bits [31:0] are architecturally mapped to AArch64 System register MAIR_EL1[63:32] when EL3 is not implemented or EL3 is using AArch64.
AArch32 System register MAIR1 bits [31:0] are architecturally mapped to AArch32 System register NMRR[31:0] when EL3 is not implemented or EL3 is using AArch64.
AArch32 System register MAIR1 bits [31:0] (MAIR1_NS) are architecturally mapped to AArch32 System register NMRR[31:0] (NMRR_NS) when EL3 is using AArch32.
AArch32 System register MAIR1 bits [31:0] (MAIR1_S) are architecturally mapped to AArch32 System register NMRR[31:0] (NMRR_S) when EL3 is using AArch32.
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to MAIR1 are UNDEFINED.
MAIR1 and NMRR are the same register, with a different view depending on the value of TTBCR.EAE:
- When it is set to 0, the register is as described in NMRR.
- When it is set to 1, the register is as described in MAIR1.
When EL3 is using AArch32, write access to MAIR1(S) is disabled when the CP15SDISABLE signal is asserted HIGH.
Attributes
MAIR1 is a 32-bit register.
Field descriptions
The MAIR1 bit assignments are:
When TTBCR.EAE == 1:
Attr<n>, bits [8(n-4)+7:8(n-4)], for n = 4 to 7
The memory attribute encoding for an AttrIndx[2:0] entry in a Long descriptor format translation table entry, where:
- AttrIndx[2:0] gives the value of <n> in Attr<n>.
- AttrIndx[2] defines which MAIR to access. Attr7 to Attr4 are in MAIR1, and Attr3 to Attr0 are in MAIR0.
Bits [7:4] are encoded as follows:
| Attr<n>[7:4] | Meaning |
|---|---|
| 0b0000 | Device memory. See encoding of Attr<n>[3:0] for the type of Device memory. |
| 0b00RW, RW not0b00 | Normal memory, Outer Write-Through Transient. |
| 0b0100 | Normal memory, Outer Non-cacheable. |
| 0b01RW, RW not0b00 | Normal memory, Outer Write-Back Transient. |
| 0b10RW | Normal memory, Outer Write-Through Non-transient. |
| 0b11RW | Normal memory, Outer Write-Back Non-transient. |
R = Outer Read-Allocate policy, W = Outer Write-Allocate policy.
The meaning of bits [3:0] depends on the value of bits [7:4]:
| Attr<n>[3:0] | Meaning when Attr<n>[7:4] is0b0000 | Meaning when Attr<n>[7:4] is not0b0000 |
|---|---|---|
| 0b0000 | Device-nGnRnE memory | UNPREDICTABLE |
| 0b00RW, RW not0b00 | UNPREDICTABLE | Normal memory, Inner Write-Through Transient |
| 0b0100 | Device-nGnRE memory | Normal memory, Inner Non-cacheable |
| 0b01RW, RW not0b00 | UNPREDICTABLE | Normal memory, Inner Write-Back Transient |
| 0b1000 | Device-nGRE memory | Normal memory, Inner Write-Through Non-transient (RW=0b00) |
| 0b10RW, RW not0b00 | UNPREDICTABLE | Normal memory, Inner Write-Through Non-transient |
| 0b1100 | Device-GRE memory | Normal memory, Inner Write-Back Non-transient (RW=0b00) |
| 0b11RW, RW not0b00 | UNPREDICTABLE | Normal memory, Inner Write-Back Non-transient |
R = Inner Read-Allocate policy, W = Inner Write-Allocate policy.
The R and W bits in some Attr<n> fields have the following meanings:
| R or W | Meaning |
|---|---|
| 0b0 | No Allocate |
| 0b1 | Allocate |
This field resets to an architecturally UNKNOWN value.
Accessing the MAIR1
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1010 | 0b0010 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T10 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T10 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TRVM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TRVM == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) then
if TTBCR.EAE == '1' then
return MAIR1_NS;
else
return NMRR_NS;
else
if TTBCR.EAE == '1' then
return MAIR1;
else
return NMRR;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && ELUsingAArch32(EL3) then
if TTBCR.EAE == '1' then
return MAIR1_NS;
else
return NMRR_NS;
else
if TTBCR.EAE == '1' then
return MAIR1;
else
return NMRR;
elsif PSTATE.EL == EL3 then
if TTBCR.EAE == '1' then
if SCR.NS == '0' then
return MAIR1_S;
else
return MAIR1_NS;
else
if SCR.NS == '0' then
return NMRR_S;
else
return NMRR_NS;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1010 | 0b0010 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T10 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T10 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TVM == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TVM == '1' then
AArch32.TakeHypTrapException(0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) then
if TTBCR.EAE == '1' then
MAIR1_NS = R[t];
else
NMRR_NS = R[t];
else
if TTBCR.EAE == '1' then
MAIR1 = R[t];
else
NMRR = R[t];
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && ELUsingAArch32(EL3) then
if TTBCR.EAE == '1' then
MAIR1_NS = R[t];
else
NMRR_NS = R[t];
else
if TTBCR.EAE == '1' then
MAIR1 = R[t];
else
NMRR = R[t];
elsif PSTATE.EL == EL3 then
if SCR.NS == '0' && CP15SDISABLE == HIGH then
UNDEFINED;
elsif SCR.NS == '0' && CP15SDISABLE2 == HIGH then
UNDEFINED;
else
if TTBCR.EAE == '1' then
if SCR.NS == '0' then
MAIR1_S = R[t];
else
MAIR1_NS = R[t];
else
if SCR.NS == '0' then
NMRR_S = R[t];
else
NMRR_NS = R[t];