SDCR, Secure Debug Control Register
The SDCR characteristics are:
Purpose
Provides EL3 configuration options for self-hosted debug, trace, and the Performance Monitors Extension.
Configuration
AArch32 System register SDCR bits [31:0] can be mapped to AArch64 System register MDCR_EL3[31:0] , but this is not architecturally mandated.
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to SDCR are UNDEFINED.
Attributes
SDCR is a 32-bit register.
Field descriptions
The SDCR bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | MTPME | TDCC | RES0 | SCCD | RES0 | EPMAD | EDAD | TTRF | STE | SPME | RES0 | SPD | RES0 | ||||||||||||||||||
Bits [31:29]
Reserved, RES0.
MTPME, bit [28]
When FEAT_MTPMU is implemented:
When FEAT_MTPMU is implemented:
Multi-threaded PMU Enable. Enables use of the PMEVTYPER<n>.MT bits.
| MTPME | Meaning |
|---|---|
| 0b0 |
FEAT_MTPMU is disabled. The Effective value of PMEVTYPER<n>.MT is zero. |
| 0b1 |
PMEVTYPER<n>.MT bits not affected by this bit. |
If FEAT_MTPMU is disabled for any other PE in the system that has the same level 1 Affinity as the PE, it is IMPLEMENTATION DEFINED whether the PE behaves as if this bit is 0.
On a Cold reset, in a system where the PE resets into EL3, this field resets to 1.
Otherwise:
Otherwise:
Reserved, RES0.
TDCC, bit [27]
When FEAT_FGT is implemented:
When FEAT_FGT is implemented:
Trap DCC. Traps use of the Debug Comms Channel in modes other than Monitor mode to Monitor mode.
| TDCC | Meaning |
|---|---|
| 0b0 |
This control does not cause any register accesses to be trapped. |
| 0b1 |
Accesses to the DCC registers in modes other than Monitor mode generate a Monitor Trap exception, unless the access also generates a higher priority exception. Traps on the DCC data transfer registers are ignored when the PE is in Debug state. |
The DCC registers trapped by this control are:
- DBGDTRRXext, DBGDTRTXext, DBGDSCRint, DBGDCCINT, and, when the PE is in Non-debug state, DBGDTRRXint and DBGDTRTXint.
When the PE is in Debug state, SDCR.TDCC does not trap any accesses to:
- DBGDTRRXint and DBGDTRTXint.
In a system where the PE resets into EL3, this field resets to an architecturally UNKNOWN value.
Otherwise:
Otherwise:
Reserved, RES0.
Bits [26:24]
Reserved, RES0.
SCCD, bit [23]
When FEAT_PMUv3p5 is implemented:
When FEAT_PMUv3p5 is implemented:
Secure Cycle Counter Disable. Prohibits PMCCNTR from counting in Secure state.
| SCCD | Meaning |
|---|---|
| 0b0 |
Cycle counting by PMCCNTR is not affected by this bit. |
| 0b1 |
Cycle counting by PMCCNTR is prohibited in Secure state. |
This bit does not affect the CPU_CYCLES event or any other event that counts cycles.
In a system where the PE resets into EL3, this field resets to 0.
Otherwise:
Otherwise:
Reserved, RES0.
Bit [22]
Reserved, RES0.
EPMAD, bit [21]
When FEAT_Debugv8p4 is implemented and FEAT_PMUv3 is implemented:
When FEAT_Debugv8p4 is implemented and FEAT_PMUv3 is implemented:
External Performance Monitors Non-secure access disable. Controls Non-secure access to Performance Monitors registers by an external debugger.
| EPMAD | Meaning |
|---|---|
| 0b0 |
Non-secure access to the Performance Monitors registers from an external debugger is permitted. |
| 0b1 |
Non-secure access to the Performance Monitors registers from an external debugger is not permitted. |
If the Performance Monitors Extension does not support external debug interface accesses this bit is RES0.
Otherwise, if EL3 is not implemented and the Effective value of SCR.NS is 0b0, then the Effective value of this field is 0b1.
In a system where the PE resets into EL3, this field resets to 0.
When FEAT_PMUv3 is implemented:
When FEAT_PMUv3 is implemented:
External Performance Monitors access disable. Controls access to Performance Monitors registers by an external debugger.
| EPMAD | Meaning |
|---|---|
| 0b0 |
Access to Performance Monitors registers from an external debugger is permitted. |
| 0b1 |
Access to Performance Monitors registers from an external debugger is not permitted, unless overridden by the IMPLEMENTATION DEFINED authentication interface. |
If the Performance Monitors Extension does not support external debug interface accesses this bit is RES0.
Otherwise, if EL3 is not implemented and the Effective value of SCR.NS is 0b0, then the Effective value of this field is 0b1.
In a system where the PE resets into EL3, this field resets to 0.
Otherwise:
Otherwise:
Reserved, RES0.
EDAD, bit [20]
When FEAT_Debugv8p4 is implemented:
When FEAT_Debugv8p4 is implemented:
External debug Non-secure access disable. Controls Non-secure access to breakpoint, watchpoint, and OSLAR_EL1 registers by an external debugger.
| EDAD | Meaning |
|---|---|
| 0b0 |
Non-secure access to debug registers from an external debugger is permitted. |
| 0b1 |
Non-secure access to breakpoint registers, watchpoint registers, and OSLAR_EL1 from an external debugger is not permitted. |
If EL3 is not implemented and the Effective value of SCR.NS is 0b0, then the Effective value of this field is 0b1.
In a system where the PE resets into EL3, this field resets to 0.
When FEAT_Debugv8p2 is implemented:
When FEAT_Debugv8p2 is implemented:
External debug access disable. Controls access to breakpoint, watchpoint, and OSLAR_EL1 registers by an external debugger.
| EDAD | Meaning |
|---|---|
| 0b0 |
Access to debug registers from an external debugger is permitted. |
| 0b1 |
Access to breakpoint registers, watchpoint registers and OSLAR_EL1 from an external debugger is not permitted, unless overridden by the IMPLEMENTATION DEFINED authentication interface. |
If EL3 is not implemented and the Effective value of SCR.NS is 0b0, then the Effective value of this field is 0b1.
In a system where the PE resets into EL3, this field resets to 0.
Otherwise:
Otherwise:
External debug access disable. Controls access to breakpoint, watchpoint, and optionally OSLAR_EL1 registers by an external debugger.
| EDAD | Meaning |
|---|---|
| 0b0 |
Access to debug registers from an external debugger is permitted. |
| 0b1 |
Access to breakpoint registers and watchpoint registers from an external debugger is not permitted, unless overridden by the IMPLEMENTATION DEFINED authentication interface. It is IMPLEMENTATION DEFINED whether access to the OSLAR_EL1 register from an external debugger is permitted or not permitted. |
If EL3 is not implemented and the Effective value of SCR.NS is 0b0, then the Effective value of this field is 0b1.
In a system where the PE resets into EL3, this field resets to 0.
TTRF, bit [19]
When FEAT_TRF is implemented:
When FEAT_TRF is implemented:
Trap Trace Filter controls. Controls whether accesses at EL2 and EL1 to the trace filter control registers are trapped to EL3.
| TTRF | Meaning |
|---|---|
| 0b0 |
Accesses to HTRFCR and TRFCR registers are not affected by this control bit. |
| 0b1 |
When not in Monitor mode, accesses to HTRFCR and TRFCR registers generate a Monitor Trap exception, unless the access generates a higher priority exception. |
In a system where the PE resets into EL3, this field resets to 0.
Otherwise:
Otherwise:
Reserved, RES0.
STE, bit [18]
When FEAT_TRF is implemented:
When FEAT_TRF is implemented:
Secure Trace Enable. This bit enables tracing in Secure state and controls the level of authentication required by an external debugger to enable external tracing.
| STE | Meaning |
|---|---|
| 0b0 |
Trace is prohibited in Secure state unless overridden by the IMPLEMENTATION DEFINED authentication interface. |
| 0b1 |
Trace in Secure state is not affected by this bit. |
This bit also controls the level of authentication required by an external debugger to enable external tracing. See 'Register controls to enable self-hosted trace'.
If EL3 is not implemented and the Effective value of SCR.NS is 0b0, the PE behaves as if this bit is set to 0b1.
In a system where the PE resets into EL3, this field resets to 0.
Otherwise:
Otherwise:
Reserved, RES0.
SPME, bit [17]
When FEAT_Debugv8p2 is implemented and FEAT_PMUv3 is implemented:
When FEAT_Debugv8p2 is implemented and FEAT_PMUv3 is implemented:
Secure Performance Monitors enable. This allows event counting in Secure state.
| SPME | Meaning |
|---|---|
| 0b0 |
Event counting prohibited in Secure state. |
| 0b1 |
Event counting allowed in Secure state. |
If EL3 is not implemented and the Effective value of SCR.NS is 0b0, then the Effective value of this bit is 0b1.
In a system where the PE resets into EL3, this field resets to 0.
When FEAT_PMUv3 is implemented:
When FEAT_PMUv3 is implemented:
Secure Performance Monitors enable. This allows event counting in Secure state.
| SPME | Meaning |
|---|---|
| 0b0 |
Event counting prohibited in Secure state, unless ExternalSecureNoninvasiveDebugEnabled() is TRUE. |
| 0b1 |
Event counting allowed in Secure state. |
If EL3 is not implemented and the Effective value of SCR.NS is 0b0, then the Effective value of this bit is 0b1.
In a system where the PE resets into EL3, this field resets to 0.
Otherwise:
Otherwise:
Reserved, RES0.
Bit [16]
Reserved, RES0.
SPD, bits [15:14]
AArch32 Secure self-hosted Privileged Debug. Enables or disables debug exceptions from EL3, other than Breakpoint Instruction exceptions
| SPD | Meaning |
|---|---|
| 0b00 |
Legacy mode. Debug exceptions from EL3 are enabled by the authentication interface. |
| 0b10 |
Secure privileged debug disabled. Debug exceptions from EL3 are disabled. |
| 0b11 |
Secure privileged debug enabled. Debug exceptions from EL3 are enabled. |
Other values are reserved, and have the CONSTRAINED UNPREDICTABLE behavior that they must have the same behavior as 0b00. Software must not rely on this property as the behavior of reserved values might change in a future revision of the architecture.
This field has no effect on Breakpoint Instruction exceptions. These are always enabled.
This field is ignored in Non-secure state.
If debug exceptions from EL3 are enabled, then debug exceptions from Secure EL0 are also enabled.
Otherwise, debug exceptions from Secure EL0 are enabled only if the value of SDER.SUIDEN is 0b1.
If EL3 is not implemented and the Effective value of SCR.NS is 0b0, then the Effective value of this field is 0b11.
In a system where the PE resets into EL3, this field resets to 0.
Bits [13:0]
Reserved, RES0.
Accessing the SDCR
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0001 | 0b0011 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T1 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif !ELUsingAArch32(EL2) && SCR_EL3.<NS,EEL2> == '01' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
UNDEFINED;
elsif PSTATE.EL == EL3 then
return SDCR;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0001 | 0b0011 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T1 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif !ELUsingAArch32(EL2) && SCR_EL3.<NS,EEL2> == '01' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif !ELUsingAArch32(EL3) && SCR_EL3.NS == '0' then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
UNDEFINED;
elsif PSTATE.EL == EL3 then
if SCR.NS == '0' && CP15SDISABLE2 == HIGH then
UNDEFINED;
else
SDCR = R[t];