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TLBTR, TLB Type Register
The TLBTR characteristics are:
Purpose
Provides information about the TLB implementation. The register must define whether the implementation provides separate instruction and data TLBs, or a unified TLB. Normally, the IMPLEMENTATION DEFINED information in this register includes the number of lockable entries in the TLB.
Configuration
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to TLBTR are UNDEFINED.
Attributes
TLBTR is a 32-bit register.
Field descriptions
The TLBTR bit assignments are:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IMPLEMENTATION DEFINED | nU | ||||||||||||||||||||||||||||||
IMPLEMENTATION DEFINED, bits [31:1]
IMPLEMENTATION DEFINED.
nU, bit [0]
Not Unified TLB. Indicates whether the implementation has a unified TLB:
| nU | Meaning |
|---|---|
| 0b0 |
Unified TLB. |
| 0b1 |
Separate Instruction and Data TLBs. |
Accessing the TLBTR
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b0000 | 0b0000 | 0b011 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID1 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID1 == '1' then
AArch32.TakeHypTrapException(0x03);
else
return TLBTR;
elsif PSTATE.EL == EL2 then
return TLBTR;
elsif PSTATE.EL == EL3 then
return TLBTR;