TRFCR, Trace Filter Control Register
The TRFCR characteristics are:
Purpose
Provides EL1 controls for Trace.
Configuration
AArch32 System register TRFCR bits [31:0] are architecturally mapped to AArch64 System register TRFCR_EL1[31:0] .
This register is present only when AArch32 is supported at any Exception level and FEAT_TRF is implemented. Otherwise, direct accesses to TRFCR are UNDEFINED.
Attributes
TRFCR is a 32-bit register.
Field descriptions
The TRFCR bit assignments are:
Bits [31:7]
Reserved, RES0.
TS, bits [6:5]
Timestamp Control. Controls which timebase is used for trace timestamps.
TS | Meaning | Applies when |
---|---|---|
0b01 |
Virtual timestamp. The traced timestamp is the physical counter value, minus the value of CNTVOFF. | |
0b10 |
Guest Physical timestamp. The traced timestamp is the physical counter value, minus the value of CNTPOFF_EL2. | When FEAT_ECV is implemented |
0b11 |
Physical timestamp. The traced timestamp is the physical counter value. |
All other values are reserved.
This field is ignored if any of the following are true:
- SelfHostedTraceEnabled() == FALSE.
- HTRFCR.TS is not 0b00.
If FEAT_ECV is implemented, the physical counter uses a fixed physical offset of zero if any of the following are true:
- When EL2 is implemented and enabled in the current Security state and is using AArch32.
- CNTHCTL_EL2.ECV is 0.
- SCR_EL3.ECVEn is 0.
- HCR_EL2.{E2H, TGE} is {1, 1}.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bits [4:2]
Reserved, RES0.
E1TRE, bit [1]
EL1 Trace Enable.
E1TRE | Meaning |
---|---|
0b0 |
Tracing is prohibited in PL1 modes. |
0b1 |
Tracing is allowed in PL1 modes. |
This field is ignored if SelfHostedTraceEnabled() == FALSE.
On a Warm reset, this field resets to 0.
E0TRE, bit [0]
EL0 Trace Enable.
E0TRE | Meaning |
---|---|
0b0 |
Tracing is prohibited at EL0. |
0b1 |
Tracing is allowed at EL0. |
This field is ignored if any of the following are true:
- SelfHostedTraceEnabled() == FALSE.
- EL2 is implemented and enabled in the current security state and HCR.TGE == 1.
On a Warm reset, this field resets to 0.
Accessing the TRFCR
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0001 | 0b0010 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SDCR.TTRF == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T1 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TTRF == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TTRF == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SDCR.TTRF == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch32.TakeMonitorTrapException(); else return TRFCR; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && ELUsingAArch32(EL3) && SDCR.TTRF == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SDCR.TTRF == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch32.TakeMonitorTrapException(); else return TRFCR; elsif PSTATE.EL == EL3 then if PSTATE.M != M32_Monitor && SDCR.TTRF == '1' then AArch32.TakeMonitorTrapException(); else return TRFCR;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0001 | 0b0010 | 0b001 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SDCR.TTRF == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T1 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TTRF == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TTRF == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SDCR.TTRF == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch32.TakeMonitorTrapException(); else TRFCR = R[t]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then UNDEFINED; elsif Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && ELUsingAArch32(EL3) && SDCR.TTRF == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TTRF == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SDCR.TTRF == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch32.TakeMonitorTrapException(); else TRFCR = R[t]; elsif PSTATE.EL == EL3 then if PSTATE.M != M32_Monitor && SDCR.TTRF == '1' then AArch32.TakeMonitorTrapException(); else TRFCR = R[t];