VPIDR, Virtualization Processor ID Register
The VPIDR characteristics are:
Purpose
Holds the value of the Virtualization Processor ID. This is the value returned by Non-secure EL1 reads of MIDR.
Configuration
AArch32 System register VPIDR bits [31:0] are architecturally mapped to AArch64 System register VPIDR_EL2[31:0] .
This register is present only when AArch32 is supported at any Exception level. Otherwise, direct accesses to VPIDR are UNDEFINED.
If EL2 is not implemented but EL3 is implemented, this register takes the value of the MIDR.
Attributes
VPIDR is a 32-bit register.
Field descriptions
The VPIDR bit assignments are:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Implementer | Variant | Architecture | PartNum | Revision |
Implementer, bits [31:24]
The Implementer code. This field must hold an implementer code that has been assigned by Arm. Assigned codes include the following:
Hex representation | ASCII representation | Implementer |
---|---|---|
0x41 | A | Arm Limited |
0x42 | B | Broadcom Corporation |
0x43 | C | Cavium Inc. |
0x44 | D | Digital Equipment Corporation |
0x49 | I | Infineon Technologies AG |
0x4D | M | Motorola or Freescale Semiconductor Inc. |
0x4E | N | NVIDIA Corporation |
0x50 | P | Applied Micro Circuits Corporation |
0x51 | Q | Qualcomm Inc. |
0x56 | V | Marvell International Ltd. |
0x69 | i | Intel Corporation |
Arm can assign codes that are not published in this manual. All values not assigned by Arm are reserved and must not be used.
In a system where the PE resets into EL2 or EL3, this field resets to the value in MIDR.Implementer.
Variant, bits [23:20]
An IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product.
In a system where the PE resets into EL2 or EL3, this field resets to the value in MIDR.Variant.
Architecture, bits [19:16]
Architecture version. Defined values are:
Architecture | Meaning |
---|---|
0b0001 |
Armv4. |
0b0010 |
Armv4T. |
0b0011 |
Armv5 (obsolete). |
0b0100 |
Armv5T. |
0b0101 |
Armv5TE. |
0b0110 |
Armv5TEJ. |
0b0111 |
Armv6. |
0b1111 |
Architectural features are individually identified in the ID_* registers, see 'ID registers'. |
All other values are reserved.
In a system where the PE resets into EL2 or EL3, this field resets to the value in MIDR.Architecture.
PartNum, bits [15:4]
An IMPLEMENTATION DEFINED primary part number for the device.
On processors implemented by Arm, if the top four bits of the primary part number are 0x0 or 0x7, the variant and architecture are encoded differently.
In a system where the PE resets into EL2 or EL3, this field resets to the value in MIDR.PartNum.
Revision, bits [3:0]
An IMPLEMENTATION DEFINED revision number for the device.
In a system where the PE resets into EL2 or EL3, this field resets to the value in MIDR.Revision.
Accessing the VPIDR
Accesses to this register use the following encodings:
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b100 | 0b0000 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then return VPIDR; elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then return MIDR; elsif SCR.NS == '0' then UNDEFINED; else return VPIDR;
MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b100 | 0b0000 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then VPIDR = R[t]; elsif PSTATE.EL == EL3 then if !HaveEL(EL2) then //no operation elsif SCR.NS == '0' then UNDEFINED; else VPIDR = R[t];
MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
coproc | opc1 | CRn | CRm | opc2 |
---|---|---|---|---|
0b1111 | 0b000 | 0b0000 | 0b0000 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) then return VPIDR_EL2<31:0>; elsif EL2Enabled() && ELUsingAArch32(EL2) then return VPIDR; else return MIDR; elsif PSTATE.EL == EL2 then return MIDR; elsif PSTATE.EL == EL3 then return MIDR;