TLBI ALLE1IS, TLB Invalidate All, EL1, Inner Shareable
The TLBI ALLE1IS characteristics are:
Purpose
Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
-
The entry is a stage 1 or stage 2 translation table entry, from any level of the translation table walk.
-
If SCR_EL3.NS is 0 and the entry would be required to translate an address using the Secure EL1&0 translation regime.
-
If SCR_EL3.NS is 1 and the entry would be required to translate an address using the Non-secure EL1&0 translation regime.
The invalidation applies to entries with any VMID.
The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction.
For the EL1&0 translation regimes, the invalidation applies to both global entries, and non-global entries with any ASID.
Configuration
There are no configuration notes.
Attributes
TLBI ALLE1IS is a 64-bit System instruction.
Field descriptions
This instruction has no applicable fields.
The value in the register specified by <Xt> is ignored.
Executing the TLBI ALLE1IS instruction
When executing this instruction Xt should be encoded as 0b11111. If the Xt field is not set to 0b11111, it is CONSTRAINED UNPREDICTABLE whether:
-
The instruction is UNDEFINED.
-
The instruction behaves as if the Xt field is set to 0b11111.
Accesses to this instruction use the following encodings:
TLBI ALLE1IS{, <Xt>}
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b01 | 0b100 | 0b1000 | 0b0011 | 0b100 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
TLBI_ALLE1IS();
elsif PSTATE.EL == EL3 then
TLBI_ALLE1IS();