TLBI VMALLE1, TLB Invalidate by VMID, All at stage 1, EL1
The TLBI VMALLE1 characteristics are:
Purpose
Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:
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The entry is a stage 1 translation table entry, from any level of the translation table walk.
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When EL2 is implemented and enabled in the Security state described by the current value of SCR_EL3.NS:
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When EL2 is not implemented or is disabled in the current Security state, the entry would be required to translate the specified VA using the EL1&0 translation regime.
The invalidation applies to the PE that executes this System instruction.
For the EL1&0 translation regimes, the invalidation applies to both global entries, and non-global entries with any ASID.
Configuration
There are no configuration notes.
Attributes
TLBI VMALLE1 is a 64-bit System instruction.
Field descriptions
This instruction has no applicable fields.
The value in the register specified by <Xt> is ignored.
Executing the TLBI VMALLE1 instruction
When executing this instruction Xt should be encoded as 0b11111. If the Xt field is not set to 0b11111, it is CONSTRAINED UNPREDICTABLE whether:
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The instruction is UNDEFINED.
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The instruction behaves as if the Xt field is set to 0b11111.
Accesses to this instruction use the following encodings:
TLBI VMALLE1{, <Xt>}
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b01 | 0b000 | 0b1000 | 0b0111 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TTLB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.TLBIVMALLE1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.FB == '1' then TLBI_VMALLE1IS(); else TLBI_VMALLE1(); elsif PSTATE.EL == EL2 then TLBI_VMALLE1(); elsif PSTATE.EL == EL3 then TLBI_VMALLE1();