CNTV_CVAL_EL0, Counter-timer Virtual Timer CompareValue register
The CNTV_CVAL_EL0 characteristics are:
Purpose
Holds the compare value for the virtual timer.
Configuration
AArch64 System register CNTV_CVAL_EL0 bits [63:0] are architecturally mapped to AArch32 System register CNTV_CVAL[63:0] .
Attributes
CNTV_CVAL_EL0 is a 64-bit register.
Field descriptions
The CNTV_CVAL_EL0 bit assignments are:
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
CompareValue | |||||||||||||||||||||||||||||||
CompareValue | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CompareValue, bits [63:0]
Holds the EL1 virtual timer CompareValue.
When CNTV_CTL_EL0.ENABLE is 1, the timer condition is met when (CNTVCT_EL0 - CompareValue) is greater than or equal to zero. This means that CompareValue acts like a 64-bit upcounter timer. When the timer condition is met:
- CNTV_CTL_EL0.ISTATUS is set to 1.
- If CNTV_CTL_EL0.IMASK is 0, an interrupt is generated.
When CNTV_CTL_EL0.ENABLE is 0, the timer condition is not met, but CNTVCT_EL0 continues to count.
If the Generic counter is implemented at a size less than 64 bits, then this field is permitted to be implemented at the same width as the counter, and the upper bits are RES0.
The value of this field is treated as zero-extended in all counter calculations.
This field resets to an architecturally UNKNOWN value.
Accessing the CNTV_CVAL_EL0
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL3 using the mnemonic CNTV_CVAL_EL0 or CNTV_CVAL_EL02 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
Accesses to this register use the following encodings:
MRS <Xt>, CNTV_CVAL_EL0
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b1110 | 0b0011 | 0b010 |
if PSTATE.EL == EL0 then if !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CNTKCTL_EL1.EL0VTEN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && CNTHCTL_EL2.EL0VTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && CNTHCTL_EL2.EL1TVT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCR_EL3.NS == '0' && IsFeatureImplemented("FEAT_SEL2") then return CNTHVS_CVAL_EL2; elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCR_EL3.NS == '1' then return CNTHV_CVAL_EL2; else return CNTV_CVAL_EL0; elsif PSTATE.EL == EL1 then if EL2Enabled() && CNTHCTL_EL2.EL1TVT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then return NVMem[0x168]; else return CNTV_CVAL_EL0; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' && SCR_EL3.NS == '0' && IsFeatureImplemented("FEAT_SEL2") then return CNTHVS_CVAL_EL2; elsif HCR_EL2.E2H == '1' && SCR_EL3.NS == '1' then return CNTHV_CVAL_EL2; else return CNTV_CVAL_EL0; elsif PSTATE.EL == EL3 then return CNTV_CVAL_EL0;
MSR CNTV_CVAL_EL0, <Xt>
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b011 | 0b1110 | 0b0011 | 0b010 |
if PSTATE.EL == EL0 then if !(EL2Enabled() && HCR_EL2.<E2H,TGE> == '11') && CNTKCTL_EL1.EL0VTEN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && CNTHCTL_EL2.EL0VTEN == '0' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && CNTHCTL_EL2.EL1TVT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCR_EL3.NS == '0' && IsFeatureImplemented("FEAT_SEL2") then CNTHVS_CVAL_EL2 = X[t]; elsif EL2Enabled() && HCR_EL2.<E2H,TGE> == '11' && SCR_EL3.NS == '1' then CNTHV_CVAL_EL2 = X[t]; else CNTV_CVAL_EL0 = X[t]; elsif PSTATE.EL == EL1 then if EL2Enabled() && CNTHCTL_EL2.EL1TVT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x168] = X[t]; else CNTV_CVAL_EL0 = X[t]; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' && SCR_EL3.NS == '0' && IsFeatureImplemented("FEAT_SEL2") then CNTHVS_CVAL_EL2 = X[t]; elsif HCR_EL2.E2H == '1' && SCR_EL3.NS == '1' then CNTHV_CVAL_EL2 = X[t]; else CNTV_CVAL_EL0 = X[t]; elsif PSTATE.EL == EL3 then CNTV_CVAL_EL0 = X[t];
MRS <Xt>, CNTV_CVAL_EL02
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b101 | 0b1110 | 0b0011 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then if EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && CNTHCTL_EL2.EL1NVVCT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else return NVMem[0x168]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then return CNTV_CVAL_EL0; else UNDEFINED; elsif PSTATE.EL == EL3 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' then return CNTV_CVAL_EL0; else UNDEFINED;
MSR CNTV_CVAL_EL02, <Xt>
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b11 | 0b101 | 0b1110 | 0b0011 | 0b010 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '101' then if EL2Enabled() && HCR_EL2.<E2H,TGE> != '11' && CNTHCTL_EL2.EL1NVVCT == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else NVMem[0x168] = X[t]; elsif EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then CNTV_CVAL_EL0 = X[t]; else UNDEFINED; elsif PSTATE.EL == EL3 then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.E2H == '1' then CNTV_CVAL_EL0 = X[t]; else UNDEFINED;