DBGVCR32_EL2, Debug Vector Catch Register
The DBGVCR32_EL2 characteristics are:
Purpose
Allows access to the AArch32 register DBGVCR from AArch64 state only. Its value has no effect on execution in AArch64 state.
Configuration
AArch64 System register DBGVCR32_EL2 bits [31:0] are architecturally mapped to AArch32 System register DBGVCR[31:0] .
This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to DBGVCR32_EL2 are UNDEFINED.
If EL2 is not implemented but EL3 is implemented, and EL1 is capable of using AArch32, then this register is not RES0.
Attributes
DBGVCR32_EL2 is a 64-bit register.
Field descriptions
The DBGVCR32_EL2 bit assignments are:
When EL3 is implemented:
Bits [63:32]
Reserved, RES0.
NSF, bit [31]
FIQ vector catch enable in Non-secure state.
The exception vector offset is 0x1C.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
NSI, bit [30]
IRQ vector catch enable in Non-secure state.
The exception vector offset is 0x18.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bit [29]
Reserved, RES0.
NSD, bit [28]
Data Abort vector catch enable in Non-secure state.
The exception vector offset is 0x10.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
NSP, bit [27]
Prefetch Abort vector catch enable in Non-secure state.
The exception vector offset is 0x0C.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
NSS, bit [26]
Supervisor Call (SVC) vector catch enable in Non-secure state.
The exception vector offset is 0x08.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
NSU, bit [25]
Undefined Instruction vector catch enable in Non-secure state.
The exception vector offset is 0x04.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bits [24:8]
Reserved, RES0.
SF, bit [7]
FIQ vector catch enable in Secure state.
The exception vector offset is 0x1C.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
SI, bit [6]
IRQ vector catch enable in Secure state.
The exception vector offset is 0x18.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bit [5]
Reserved, RES0.
SD, bit [4]
Data Abort vector catch enable in Secure state.
The exception vector offset is 0x10.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
SP, bit [3]
Prefetch Abort vector catch enable in Secure state.
The exception vector offset is 0x0C.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
SS, bit [2]
Supervisor Call (SVC) vector catch enable in Secure state.
The exception vector offset is 0x08.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
SU, bit [1]
Undefined Instruction vector catch enable in Secure state.
The exception vector offset is 0x04.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bit [0]
Reserved, RES0.
When EL3 is not implemented:
Bits [63:8]
Reserved, RES0.
F, bit [7]
FIQ vector catch enable.
The exception vector offset is 0x1C.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
I, bit [6]
IRQ vector catch enable.
The exception vector offset is 0x18.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bit [5]
Reserved, RES0.
D, bit [4]
Data Abort vector catch enable.
The exception vector offset is 0x10.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
P, bit [3]
Prefetch Abort vector catch enable.
The exception vector offset 0x0C.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
S, bit [2]
Supervisor Call (SVC) vector catch enable.
The exception vector offset is 0x08.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
U, bit [1]
Undefined Instruction vector catch enable.
The exception vector offset is 0x04.
On a Warm reset, this field resets to an architecturally UNKNOWN value.
Bit [0]
Reserved, RES0.
Accessing the DBGVCR32_EL2
Accesses to this register use the following encodings:
MRS <Xt>, DBGVCR32_EL2
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b100 | 0b0000 | 0b0111 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else return DBGVCR32_EL2; elsif PSTATE.EL == EL3 then return DBGVCR32_EL2;
MSR DBGVCR32_EL2, <Xt>
op0 | op1 | CRn | CRm | op2 |
---|---|---|---|---|
0b10 | 0b100 | 0b0000 | 0b0111 | 0b000 |
if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && MDCR_EL3.TDA == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TDA == '1' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else DBGVCR32_EL2 = X[t]; elsif PSTATE.EL == EL3 then DBGVCR32_EL2 = X[t];