ELR_EL2, Exception Link Register (EL2)
The ELR_EL2 characteristics are:
Purpose
When taking an exception to EL2, holds the address to return to.
Configuration
AArch64 System register ELR_EL2 bits [31:0] are architecturally mapped to AArch32 System register ELR_hyp[31:0] .
This register has no effect if EL2 is not enabled in the current Security state.
Attributes
ELR_EL2 is a 64-bit register.
Field descriptions
The ELR_EL2 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| Return address | |||||||||||||||||||||||||||||||
| Return address | |||||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:0]
Return address.
An exception return from EL2 using AArch64 makes ELR_EL2 become UNKNOWN.
When EL2 is in AArch32 Execution state and an exception is taken from EL0, EL1, or EL2 to EL3 and AArch64 execution, the upper 32-bits of ELR_EL2 are either set to 0 or hold the same value that they did before AArch32 execution. Which option is adopted is determined by an implementation, and might vary dynamically within an implementation. Correspondingly software must regard the value as being an UNKNOWN choice between the two values.
This field resets to an architecturally UNKNOWN value.
Accessing the ELR_EL2
When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic ELR_EL2 or ELR_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.
Accesses to this register use the following encodings:
MRS <Xt>, ELR_EL2
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0100 | 0b0000 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then
return ELR_EL1;
elsif EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
return ELR_EL2;
elsif PSTATE.EL == EL3 then
return ELR_EL2;
MSR ELR_EL2, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b100 | 0b0100 | 0b0000 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.<NV2,NV> == '11' then
ELR_EL1 = X[t];
elsif EL2Enabled() && HCR_EL2.NV == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
UNDEFINED;
elsif PSTATE.EL == EL2 then
ELR_EL2 = X[t];
elsif PSTATE.EL == EL3 then
ELR_EL2 = X[t];
MRS <Xt>, ELR_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0100 | 0b0000 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.<NV2,NV1> == '01' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then
return NVMem[0x230];
else
return ELR_EL1;
elsif PSTATE.EL == EL2 then
if HCR_EL2.E2H == '1' then
return ELR_EL2;
else
return ELR_EL1;
elsif PSTATE.EL == EL3 then
return ELR_EL1;
MSR ELR_EL1, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0100 | 0b0000 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && HCR_EL2.<NV2,NV1> == '01' then
AArch64.SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then
NVMem[0x230] = X[t];
else
ELR_EL1 = X[t];
elsif PSTATE.EL == EL2 then
if HCR_EL2.E2H == '1' then
ELR_EL2 = X[t];
else
ELR_EL1 = X[t];
elsif PSTATE.EL == EL3 then
ELR_EL1 = X[t];