MPAM0_EL1, MPAM0 Register (EL1)
The MPAM0_EL1 characteristics are:
Purpose
Holds information to generate MPAM labels for memory requests when executing at EL0. When EL2 is present and enabled, the MPAM virtualization option is present, MPAMHCR_EL2.GSTAPP_PLK == 1 and HCR_EL2.TGE == 0, MPAM1_EL1 is used instead of MPAM0_EL1 to generate MPAM information to label memory requests.
If EL2 is present and enabled, and HCR_EL2.E2H == 0 or HCR_EL2.TGE == 0, the MPAM virtualization option is present and MPAMHCR_EL2.EL0_VPMEN == 1, then MPAM PARTIDs in MPAM0_EL1 are virtual and mapped into physical PARTIDs for the current Security state.
Configuration
This register is present only when FEAT_MPAM is implemented. Otherwise, direct accesses to MPAM0_EL1 are UNDEFINED.
Attributes
MPAM0_EL1 is a 64-bit register.
Field descriptions
The MPAM0_EL1 bit assignments are:
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| RES0 | PMG_D | PMG_I | |||||||||||||||||||||||||||||
| PARTID_D | PARTID_I | ||||||||||||||||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits [63:48]
Reserved, RES0.
PMG_D, bits [47:40]
Performance monitoring group property for PARTID_D.
This field resets to an architecturally UNKNOWN value.
PMG_I, bits [39:32]
Performance monitoring group property for PARTID_I.
This field resets to an architecturally UNKNOWN value.
PARTID_D, bits [31:16]
Partition ID for data accesses, including load and store accesses, made from EL0.
This field resets to an architecturally UNKNOWN value.
PARTID_I, bits [15:0]
Partition ID for instruction accesses made from EL0.
This field resets to an architecturally UNKNOWN value.
Accessing the MPAM0_EL1
None of the fields in this register are permitted to be cached in a TLB.
Accesses to this register use the following encodings:
MRS <Xt>, MPAM0_EL1
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1010 | 0b0101 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
elsif EL2Enabled() && MPAM2_EL2.TRAPMPAM0EL1 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
return MPAM0_EL1;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
return MPAM0_EL1;
elsif PSTATE.EL == EL3 then
return MPAM0_EL1;
MSR MPAM0_EL1, <Xt>
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b1010 | 0b0101 | 0b001 |
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
elsif EL2Enabled() && MPAM2_EL2.TRAPMPAM0EL1 == '1' then
AArch64.SystemAccessTrap(EL2, 0x18);
else
MPAM0_EL1 = X[t];
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && MPAM3_EL3.TRAPLOWER == '1' then
if Halted() && EDSCR.SDD == '1' then
UNDEFINED;
else
AArch64.SystemAccessTrap(EL3, 0x18);
else
MPAM0_EL1 = X[t];
elsif PSTATE.EL == EL3 then
MPAM0_EL1 = X[t];